Merge branch 'development' of

[Mograsim.git] / net.mograsim.machine / src / net / mograsim / machine / standard / memory / CoreWordAddressableMemory.java

diff --git a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
index f7dd982..addb34c 100644 (file)
--- a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
+++ b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
@@ -4,9 +4,12 @@ import java.util.List;
 
 import net.mograsim.logic.core.components.BasicCoreComponent;
 import net.mograsim.logic.core.timeline.Timeline;
+import net.mograsim.logic.core.timeline.TimelineEventHandler;
 import net.mograsim.logic.core.types.Bit;
+import net.mograsim.logic.core.types.BitVector;
 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
+import net.mograsim.machine.MainMemory;
 import net.mograsim.machine.MainMemoryDefinition;
 
 /**
@@ -14,7 +17,7 @@ import net.mograsim.machine.MainMemoryDefinition;
  */
 public class CoreWordAddressableMemory extends BasicCoreComponent
 {
-       private final WordAddressableMemory memory;
+       private final MainMemory memory;
        private final static Bit read = Bit.ONE;
 
        private ReadWriteEnd data;
@@ -26,10 +29,11 @@ public class CoreWordAddressableMemory extends BasicCoreComponent
         * @param rWBit   The value of the 0th bit dictates the mode: 0: Write, 1: Read
         * @param address The bits of this ReadEnd address the memory cell to read/write
         */
-       public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
+       public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemory memory, ReadWriteEnd data,
                        ReadEnd rWBit, ReadEnd address, ReadEnd clock)
        {
                super(timeline, processTime);
+               MainMemoryDefinition definition = memory.getDefinition();
                if(data.width() != definition.getCellWidth())
                        throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
                if(rWBit.width() != 1)
@@ -45,29 +49,35 @@ public class CoreWordAddressableMemory extends BasicCoreComponent
                address.registerObserver(this);
                clock.registerObserver(this);
                
-               memory = new WordAddressableMemory(definition);
+               this.memory = memory;
        }
 
        @Override
-       protected void compute()
+       protected TimelineEventHandler compute()
        {
                if(clock.getValue() != Bit.ONE)
-                       return;
+                       return null;
+               
                if (!address.hasNumericValue())
                {
                        if (read.equals(rWBit.getValue()))
-                               data.feedSignals(Bit.U.toVector(data.width()));
-                       else
-                               data.clearSignals();
-                       return;
+                               return e -> data.feedSignals(Bit.U.toVector(data.width()));
+                       return e -> data.clearSignals();
                }
                long addressed = address.getUnsignedValue();
                if (read.equals(rWBit.getValue()))
-                       data.feedSignals(memory.getCell(addressed));
+               {
+                       BitVector storedData = memory.getCell(addressed);
+                       return e -> data.feedSignals(storedData);
+               }
                else
                {
-                       data.clearSignals();
-                       memory.setCell(addressed, data.getValues());
+                       BitVector transData = data.getValues();
+                       return e ->
+                       {
+                               data.clearSignals();
+                               memory.setCell(addressed, transData);
+                       };
                }
        }