Removed unneccessary clock input for memory components

[Mograsim.git] / net.mograsim.machine / src / net / mograsim / machine / standard / memory / CoreWordAddressableMemory.java

diff --git a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
index 8181283..afad26a 100644 (file)
--- a/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
+++ b/net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
@@ -9,6 +9,7 @@ import net.mograsim.logic.core.types.Bit;
 import net.mograsim.logic.core.types.BitVector;
 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
+import net.mograsim.machine.MainMemory;
 import net.mograsim.machine.MainMemoryDefinition;
 
 /**
@@ -16,11 +17,11 @@ import net.mograsim.machine.MainMemoryDefinition;
  */
 public class CoreWordAddressableMemory extends BasicCoreComponent
 {
-       private final WordAddressableMemory memory;
+       private final MainMemory memory;
        private final static Bit read = Bit.ONE;
 
        private ReadWriteEnd data;
-       private ReadEnd rWBit, address, clock;
+       private ReadEnd rWBit, address;
 
        /**
         * @param data    The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
@@ -28,10 +29,11 @@ public class CoreWordAddressableMemory extends BasicCoreComponent
         * @param rWBit   The value of the 0th bit dictates the mode: 0: Write, 1: Read
         * @param address The bits of this ReadEnd address the memory cell to read/write
         */
-       public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
-                       ReadEnd rWBit, ReadEnd address, ReadEnd clock)
+       public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemory memory, ReadWriteEnd data,
+                       ReadEnd rWBit, ReadEnd address)
        {
                super(timeline, processTime);
+               MainMemoryDefinition definition = memory.getDefinition();
                if(data.width() != definition.getCellWidth())
                        throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
                if(rWBit.width() != 1)
@@ -41,25 +43,20 @@ public class CoreWordAddressableMemory extends BasicCoreComponent
                this.data = data;
                this.rWBit = rWBit;
                this.address = address;
-               this.clock = clock;
                data.registerObserver(this);
                rWBit.registerObserver(this);
                address.registerObserver(this);
-               clock.registerObserver(this);
                
-               memory = new WordAddressableMemory(definition);
+               this.memory = memory;
        }
 
        @Override
        protected TimelineEventHandler compute()
        {
-               if(clock.getValue() != Bit.ONE)
-                       return null;
-               
                if (!address.hasNumericValue())
                {
                        if (read.equals(rWBit.getValue()))
-                               return e -> data.feedSignals(Bit.U.toVector(data.width()));
+                               return e -> data.feedSignals(Bit.U.toVector(data.width()));//TODO don't always feed U, but decide to feed X or U.
                        return e -> data.clearSignals();
                }
                long addressed = address.getUnsignedValue();