ModelComponentToVerilogConverter can now convert TriStateBuffers
[Mograsim.git] / plugins / net.mograsim.logic.model.verilog / src / net / mograsim / logic / model / verilog / converter / ModelComponentToVerilogComponentDeclarationMapping.java
index 5a230db..b05e152 100644 (file)
@@ -1,11 +1,12 @@
 package net.mograsim.logic.model.verilog.converter;
 
 import java.util.ArrayList;
+import java.util.HashMap;
+import java.util.HashSet;
 import java.util.List;
 import java.util.Map;
 import java.util.Objects;
 import java.util.Set;
-import java.util.function.Function;
 import java.util.stream.Collectors;
 
 import com.google.gson.JsonElement;
@@ -20,6 +21,7 @@ public class ModelComponentToVerilogComponentDeclarationMapping
        private final VerilogComponentDeclaration verilogComponentDeclaration;
        private final Set<VerilogEmulatedModelPin> pinMapping;
 
+       private final Set<Set<PinNameBit>> internallyConnectedPins;
        private final Map<PinNameBit, VerilogEmulatedModelPin> prePinMapping;
        private final Map<PinNameBit, VerilogEmulatedModelPin> outPinMapping;
        private final Map<PinNameBit, VerilogEmulatedModelPin> resPinMapping;
@@ -35,6 +37,7 @@ public class ModelComponentToVerilogComponentDeclarationMapping
 
                this.reversePinMapping = checkAndCalculateReversePinMapping();
 
+               this.internallyConnectedPins = calculateInternallyConnectedPins();
                this.prePinMapping = filterPinMapping(Type.PRE);
                this.outPinMapping = filterPinMapping(Type.OUT);
                this.resPinMapping = filterPinMapping(Type.RES);
@@ -45,8 +48,15 @@ public class ModelComponentToVerilogComponentDeclarationMapping
                List<VerilogEmulatedModelPin> reverseMapping = new ArrayList<>(pinMapping.size());
                for (int i = 0; i < pinMapping.size(); i++)
                        reverseMapping.add(null);
+               Map<Type, Set<PinNameBit>> usedPinNameBits = new HashMap<>();
+               for (Type t : Type.values())
+                       usedPinNameBits.put(t, new HashSet<>());
                for (VerilogEmulatedModelPin verilogEmulatedModelPin : pinMapping)
                {
+                       // TODO check if pre, out, res pins are consistent with each other
+                       for (PinNameBit pinbit : verilogEmulatedModelPin.getPinbits())
+                               if (!usedPinNameBits.get(verilogEmulatedModelPin.getType()).add(pinbit))
+                                       throw new IllegalArgumentException("Pinbit occurs twice: " + pinbit);
                        int verilogPinIndex = verilogEmulatedModelPin.getPortIndex();
                        if (verilogComponentDeclaration.getIOPorts().get(verilogPinIndex) != verilogEmulatedModelPin.getVerilogPort())
                                throw new IllegalArgumentException("Incorrect IO port index for port: " + verilogEmulatedModelPin);
@@ -60,10 +70,19 @@ public class ModelComponentToVerilogComponentDeclarationMapping
                return reverseMapping;
        }
 
+       private Set<Set<PinNameBit>> calculateInternallyConnectedPins()
+       {
+               return pinMapping.stream().map(VerilogEmulatedModelPin::getPinbits).collect(Collectors.toUnmodifiableSet());
+       }
+
        private Map<PinNameBit, VerilogEmulatedModelPin> filterPinMapping(Type filteredType)
        {
-               return pinMapping.stream().filter(p -> p.getType() == filteredType)
-                               .collect(Collectors.toMap(VerilogEmulatedModelPin::getPinbit, Function.identity()));
+               Map<PinNameBit, VerilogEmulatedModelPin> result = new HashMap<>();
+               for (VerilogEmulatedModelPin p : pinMapping)
+                       if (p.getType() == filteredType)
+                               for (PinNameBit pinbit : p.getPinbits())
+                                       result.put(pinbit, p);
+               return Map.copyOf(result);
        }
 
        public String getModelComponentID()
@@ -81,6 +100,11 @@ public class ModelComponentToVerilogComponentDeclarationMapping
                return verilogComponentDeclaration;
        }
 
+       public Set<Set<PinNameBit>> getInternallyConnectedPins()
+       {
+               return internallyConnectedPins;
+       }
+
        public Set<VerilogEmulatedModelPin> getPinMapping()
        {
                return pinMapping;
@@ -112,6 +136,7 @@ public class ModelComponentToVerilogComponentDeclarationMapping
                final int prime = 31;
                int result = 1;
                result = prime * result + ((modelComponentID == null) ? 0 : modelComponentID.hashCode());
+               result = prime * result + ((modelComponentParams == null) ? 0 : modelComponentParams.hashCode());
                result = prime * result + ((pinMapping == null) ? 0 : pinMapping.hashCode());
                result = prime * result + ((verilogComponentDeclaration == null) ? 0 : verilogComponentDeclaration.hashCode());
                return result;
@@ -133,6 +158,12 @@ public class ModelComponentToVerilogComponentDeclarationMapping
                                return false;
                } else if (!modelComponentID.equals(other.modelComponentID))
                        return false;
+               if (modelComponentParams == null)
+               {
+                       if (other.modelComponentParams != null)
+                               return false;
+               } else if (!modelComponentParams.equals(other.modelComponentParams))
+                       return false;
                if (pinMapping == null)
                {
                        if (other.pinMapping != null)