package net.mograsim.logic.model.verilog.model.signals;
-public class Wire extends NamedSignal
+public class Wire extends Signal
{
public Wire(String name, int width)
{
public String toDeclarationVerilogCode()
{
- return "wire [" + getWidth() + ":0] " + getName() + ";";
+ return "wire [" + (getWidth() - 1) + ":0] " + getName() + ";";
}
}