Completion of ReadEnd and ReadWriteEnd addition
[Mograsim.git] / era.mi / src / era / mi / logic / wires / Wire.java
2019-05-24 Fabian StemmlerCompletion of ReadEnd and ReadWriteEnd addition
2019-05-24 Fabian StemmlerWireEnd functionality split into ReadEnd and ReadWriteEnd
2019-05-20 Daniel KirschtenMerged SampleERCP into master
2019-05-20 Daniel KirschtenMerged logicui into master
2019-05-20 Daniel KirschtenMerged logic into master
2019-05-20 Christian FemersExchanged all Bit[] by BitVector, tests work
2019-05-20 Christian FemersIntegrated new types, tests still work, not used yet
2019-05-20 Fabian Stemmlernew WireEnds as in/outputs are now initialized with...
2019-05-20 Fabian StemmlerCleanup
2019-05-20 Fabian StemmlerMerge logic of origin into logic
2019-05-20 Fabian StemmlerWireArray(Input) is now Wire(End); all in-/outputs...