Delete REQUIREMENTS.MD because documentation and reports are now in the docs branch...
[Mograsim.git] / era.mi /
2019-05-20 Daniel KirschtenFixed GUITest: WireEnds used as outputs were created...
2019-05-20 Daniel KirschtenRestored era.mi/.project
2019-05-20 Daniel KirschtenMerged SampleERCP into master
2019-05-20 Daniel KirschtenMerged logicui into master
2019-05-20 Daniel KirschtenMerged logic into master
2019-05-20 Christian FemersExchanged all Bit[] by BitVector, tests work
2019-05-20 Christian FemersIntegrated new types, tests still work, not used yet
2019-05-20 Fabian Stemmlernew WireEnds as in/outputs are now initialized with...
2019-05-20 Fabian StemmlerCleanup
2019-05-20 Fabian StemmlerMerge logic of origin into logic
2019-05-20 Fabian StemmlerWireArray(Input) is now Wire(End); all in-/outputs...
2019-05-19 Christian FemersDid some clean up
2019-05-19 Christian FemersFixed calculations concerning U, tests work now just...
2019-05-19 Christian FemersMade Connector an Component and more useful
2019-05-19 Daniel KirschtenMade formatting uniform - commit for logic
2019-05-18 Christian FemersWireArrayEnd now created with U and GUITest supports U
2019-05-18 Christian FemersSet formatting save action
2019-05-18 Fabian StemmlerAdded project specific format; Default values in WireAr...
2019-05-18 Fabian StemmlerReformatted everything. Eclipse built-in Linewrapping...
2019-05-15 Daniel KirschtenAdded nextEventTime(); added NewEventListeners
2019-05-15 Daniel KirschtenMade ManualSwitch non-final to make GUIManualSwitch...
2019-05-15 Christian FemersAdded 'U' to Bit and made code IEEE 1164 compliant...
2019-05-15 Daniel KirschtenMade ManualSwitch non-final to make GUIManualSwitch...
2019-05-14 Daniel KirschtenNew inner-project dependency management - commit for...
2019-05-14 Daniel KirschtenNew inner-project dependency management - commit for...
2019-05-14 Daniel KirschtenRemoved obsolete era.mi in master branch
2019-05-14 Christian Femersajusted or() behaviour when Z is input
2019-05-14 Christian FemersAdded GUITest, ManualSwitch and one method to Timeline
2019-05-13 Fabian Stemmlerlogic gates and, or and xor now take an arbitrary amoun...
2019-05-12 Fabian Stemmleradded demux; added getAllInputs() and getAllOutputs...
2019-05-12 Fabian Stemmleradded more doc to Timeline; added functionality to Bit
2019-05-11 Christian Femersfixed Connector and added some useful methods to WireAr...
2019-05-11 Fabian StemmlerCleaned up ComponentTest.
2019-05-11 Fabian StemmlerRemoved Mapper class.
2019-05-10 Fabian StemmlerFixed Merger, Mux, Splitter: onedirectional again....
2019-05-10 Fabian Stemmlerbin deleted and ignored.
2019-05-10 Christian Femersadded some classes that improve testing experience
2019-05-10 Christian Femersadded some convenience methods that make our lives...
2019-05-10 Daniel KirschtenMerge branch 'wire_array_inputs_update'
2019-05-10 Fabian StemmlerWire concept was changed to accommodate multiple inputs...
2019-05-07 Fabian StemmlerAdded era.mi; Project containing provisional simulator...