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2019-05-24	Fabian Stemmler	WireEnd functionality split into ReadEnd and ReadWriteEnd	commit \| commitdiff \| tree
2019-05-20	Fabian Stemmler	new WireEnds as in/outputs are now initialized with...	commit \| commitdiff \| tree
2019-05-20	Fabian Stemmler	Cleanup	commit \| commitdiff \| tree
2019-05-20	Fabian Stemmler	Merge logic of origin into logic	commit \| commitdiff \| tree
2019-05-20	Fabian Stemmler	WireArray(Input) is now Wire(End); all in-/outputs...	commit \| commitdiff \| tree
2019-05-18	Fabian Stemmler	Added project specific format; Default values in WireArray...	commit \| commitdiff \| tree
2019-05-18	Fabian Stemmler	Reformatted everything. Eclipse built-in Linewrapping...	commit \| commitdiff \| tree
2019-05-13	Fabian Stemmler	logic gates and, or and xor now take an arbitrary amount...	commit \| commitdiff \| tree
2019-05-12	Fabian Stemmler	added demux; added getAllInputs() and getAllOutputs...	commit \| commitdiff \| tree
2019-05-12	Fabian Stemmler	added more doc to Timeline; added functionality to Bit	commit \| commitdiff \| tree
2019-05-11	Fabian Stemmler	Cleaned up ComponentTest.	commit \| commitdiff \| tree
2019-05-11	Fabian Stemmler	Removed Mapper class.	commit \| commitdiff \| tree
2019-05-10	Fabian Stemmler	Fixed Merger, Mux, Splitter: onedirectional again....	commit \| commitdiff \| tree
2019-05-10	Fabian Stemmler	bin deleted and ignored.	commit \| commitdiff \| tree
2019-05-10	Fabian Stemmler	Wire concept was changed to accommodate multiple inputs...	commit \| commitdiff \| tree
2019-05-07	Fabian Stemmler	Added era.mi; Project containing provisional simulator...	commit \| commitdiff \| tree
2019-05-07	Fabian Stemmler	Added era.mi; Project containing provisional simulator...	commit \| commitdiff \| tree

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