Fixed a bug in Am2900; created dlatch8/80; relayouted some components

[Mograsim.git] / net.mograsim.logic.model / src / net / mograsim / logic / model / modeladapter / componentadapters / SimpleGateAdapter.java

diff --git a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java
index 80830bd..c38883e 100644 (file)
--- a/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java
+++ b/net.mograsim.logic.model/src/net/mograsim/logic/model/modeladapter/componentadapters/SimpleGateAdapter.java
@@ -9,7 +9,7 @@ import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
 import net.mograsim.logic.model.model.components.atomic.SimpleRectangularModelGate;
 import net.mograsim.logic.model.model.wires.Pin;
-import net.mograsim.logic.model.modeladapter.LogicModelParameters;
+import net.mograsim.logic.model.modeladapter.CoreModelParameters;
 
 public class SimpleGateAdapter<G extends SimpleRectangularModelGate> implements ComponentAdapter<G>
 {
@@ -29,8 +29,7 @@ public class SimpleGateAdapter<G extends SimpleRectangularModelGate> implements
        }
 
        @Override
-       public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, G modelComponent,
-                       Map<Pin, CoreWire> logicWiresPerPin)
+       public void createAndLinkComponent(Timeline timeline, CoreModelParameters params, G modelComponent, Map<Pin, CoreWire> logicWiresPerPin)
        {
                ReadWriteEnd out = logicWiresPerPin.get(modelComponent.getPin("Y")).createReadWriteEnd();