import net.mograsim.logic.core.types.BitVector;
import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
+import net.mograsim.machine.MainMemory;
import net.mograsim.machine.MainMemoryDefinition;
/**
*/
public class CoreWordAddressableMemory extends BasicCoreComponent
{
- private final WordAddressableMemory memory;
+ private final MainMemory memory;
private final static Bit read = Bit.ONE;
private ReadWriteEnd data;
- private ReadEnd rWBit, address, clock;
+ private ReadEnd rWBit, address;
/**
* @param data The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
* @param rWBit The value of the 0th bit dictates the mode: 0: Write, 1: Read
* @param address The bits of this ReadEnd address the memory cell to read/write
*/
- public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
- ReadEnd rWBit, ReadEnd address, ReadEnd clock)
+ public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemory memory, ReadWriteEnd data, ReadEnd rWBit,
+ ReadEnd address)
{
super(timeline, processTime);
- if(data.width() != definition.getCellWidth())
- throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
- if(rWBit.width() != 1)
- throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
- if(address.width() != definition.getMemoryAddressBits())
- throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width()));
+ MainMemoryDefinition definition = memory.getDefinition();
+ if (data.width() != definition.getCellWidth())
+ throw new IllegalArgumentException(
+ String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d",
+ definition.getCellWidth(), data.width()));
+ if (rWBit.width() != 1)
+ throw new IllegalArgumentException(
+ String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
+ if (address.width() != definition.getMemoryAddressBits())
+ throw new IllegalArgumentException(
+ String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d",
+ definition.getMemoryAddressBits(), address.width()));
+ this.memory = memory;
this.data = data;
this.rWBit = rWBit;
this.address = address;
- this.clock = clock;
+ memory.registerObserver(a -> update());
data.registerObserver(this);
rWBit.registerObserver(this);
address.registerObserver(this);
- clock.registerObserver(this);
-
- memory = new WordAddressableMemory(definition);
}
@Override
protected TimelineEventHandler compute()
{
- if(clock.getValue() != Bit.ONE)
- return null;
-
- if (!address.hasNumericValue())
+ if (!address.getValues().isBinary())
{
if (read.equals(rWBit.getValue()))
- return e -> data.feedSignals(Bit.U.toVector(data.width()));
+ return e -> data.feedSignals(Bit.U.toVector(data.width()));// TODO don't always feed U, but decide to feed X or U.
return e -> data.clearSignals();
}
- long addressed = address.getUnsignedValue();
+ long addressed = address.getValues().getUnsignedValueLong();
if (read.equals(rWBit.getValue()))
{
BitVector storedData = memory.getCell(addressed);
return e -> data.feedSignals(storedData);
}
- else
+ BitVector transData = data.getValues();
+ if (transData.equals(memory.getCell(addressed)))
+ return null;
+ return e ->
{
- BitVector transData = data.getValues();
- return e ->
- {
- data.clearSignals();
- memory.setCell(addressed, transData);
- };
- }
+ data.clearSignals();
+ memory.setCell(addressed, transData);
+ };
}
@Override