Reserialized components
[Mograsim.git] / plugins / net.mograsim.logic.model.am2900 / components / net / mograsim / logic / model / am2900 / components / _rsLatch.json
index 7a0b4b2..8307be3 100644 (file)
@@ -89,7 +89,7 @@
           "compName": "_submodelinterface",
           "pinName": "_Q"
         },
-        "name": "_q",
+        "name": "unnamedWire#0",
         "path": []
       },
       {
           "compName": "_submodelinterface",
           "pinName": "Q"
         },
-        "name": "q",
+        "name": "unnamedWire#1",
         "path": [
           {
             "x": 35.0,
           "compName": "NandGate#0",
           "pinName": "A"
         },
-        "name": "unnamedWire#0",
+        "name": "unnamedWire#2",
         "path": []
       },
       {
           "compName": "NandGate#1",
           "pinName": "B"
         },
-        "name": "unnamedWire#1",
+        "name": "unnamedWire#3",
         "path": [
           {
             "x": 35.0,
           "compName": "WireCrossPoint#0",
           "pinName": ""
         },
-        "name": "unnamedWire#2",
+        "name": "unnamedWire#4",
         "path": []
       },
       {
           "compName": "WireCrossPoint#1",
           "pinName": ""
         },
-        "name": "unnamedWire#3",
+        "name": "unnamedWire#5",
         "path": [
           {
             "x": 65.0,
           "compName": "NandGate#1",
           "pinName": "A"
         },
-        "name": "unnamedWire#4",
+        "name": "unnamedWire#6",
         "path": []
       },
       {
           "compName": "NandGate#0",
           "pinName": "B"
         },
-        "name": "unnamedWire#5",
+        "name": "unnamedWire#7",
         "path": [
           {
             "x": 65.0,
         "id": "wireForcing",
         "params": {
           "wiresToForce": [
-            "q"
+            "unnamedWire#1"
           ],
           "wiresToForceInverted": [
-            "_q"
+            "unnamedWire#0"
           ]
         }
       }