Improvements in the ModelComponentToVerilogConverter:

[Mograsim.git] / plugins / net.mograsim.logic.model.verilog / src / net / mograsim / logic / model / verilog / model / VerilogComponentDeclaration.java

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentDeclaration.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentDeclaration.java
index bd5b018..ef6430a 100644 (file)
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentDeclaration.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentDeclaration.java
@@ -5,6 +5,8 @@ import java.util.List;
 import java.util.Objects;
 import java.util.Set;
 
+import net.mograsim.logic.model.verilog.model.signals.IOPort;
+
 public class VerilogComponentDeclaration
 {
        private final String id;