ModelComponentToVerilogConverter can now convert TriStateBuffers

[Mograsim.git] / plugins / net.mograsim.logic.model.verilog / src / net / mograsim / logic / model / verilog / model / statements / Assign.java

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Assign.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Assign.java
index e6036f0..2dd7ae0 100644 (file)
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Assign.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Assign.java
@@ -4,16 +4,15 @@ import java.util.Objects;
 import java.util.Set;
 
 import net.mograsim.logic.model.verilog.model.expressions.Expression;
-import net.mograsim.logic.model.verilog.model.signals.NamedSignal;
 import net.mograsim.logic.model.verilog.model.signals.Signal;
 import net.mograsim.logic.model.verilog.utils.CollectionsUtils;
 
 public class Assign extends Statement
 {
-       private final NamedSignal target;
+       private final Signal target;
        private final Expression source;
 
-       public Assign(NamedSignal target, Expression source)
+       public Assign(Signal target, Expression source)
        {
                this.target = Objects.requireNonNull(target);
                this.source = Objects.requireNonNull(source);