Handing through rst and clk signals (still very ugly)

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java
index a7a9de2..3dead22 100644 (file)
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java
@@ -58,7 +58,10 @@ public class VerilogComponentImplementation
                StringBuilder sb = new StringBuilder();
 
                sb.append("module " + declaration.getID());
-               sb.append(declaration.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode).collect(Collectors.joining(", ", "(", ")")));
+               // TODO handle rst / clk more cleanly.
+               // Also in CompenentReference
+               sb.append(declaration.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode)
+                               .collect(Collectors.joining(", ", "(input rst,input clk,", ")")));
                sb.append(";\n\n");
 
                for (Statement statement : statements)

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java
index dcce760..94a214e 100644 (file)
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java
@@ -59,7 +59,8 @@ public class ComponentReference extends Statement
                StringBuilder sb = new StringBuilder();
 
                sb.append(referencedComponent.getID() + " " + name);
-               sb.append(arguments.stream().map(Expression::toVerilogCode).collect(Collectors.joining(", ", "(", ")")));
+               // TODO handle rst / clk more cleanly; see VerilogCompenentImplementation
+               sb.append(arguments.stream().map(Expression::toVerilogCode).collect(Collectors.joining(", ", "(rst,clk,", ")")));
                sb.append(";");
 
                return sb.toString();