Merge branch 'development' of
authorFabian Stemmler <stemmler@in.tum.de>
Fri, 13 Sep 2019 14:16:07 +0000 (16:16 +0200)
committerFabian Stemmler <stemmler@in.tum.de>
Fri, 13 Sep 2019 14:16:07 +0000 (16:16 +0200)
https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into
development

Conflicts:
net.mograsim.machine/src/net/mograsim/machine/standard/memory/ModelMemoryWA.java
net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java

1  2 
net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java
net.mograsim.machine/src/net/mograsim/machine/standard/memory/ModelMemoryWA.java

index f7dd982,0000000..8181283
mode 100644,000000..100644
--- /dev/null
@@@ -1,85 -1,0 +1,93 @@@
-       protected void compute()
 +package net.mograsim.machine.standard.memory;
 +
 +import java.util.List;
 +
 +import net.mograsim.logic.core.components.BasicCoreComponent;
 +import net.mograsim.logic.core.timeline.Timeline;
++import net.mograsim.logic.core.timeline.TimelineEventHandler;
 +import net.mograsim.logic.core.types.Bit;
++import net.mograsim.logic.core.types.BitVector;
 +import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
 +import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
 +import net.mograsim.machine.MainMemoryDefinition;
 +
 +/**
 + * A memory component that only allows access to words of a specific width
 + */
 +public class CoreWordAddressableMemory extends BasicCoreComponent
 +{
 +      private final WordAddressableMemory memory;
 +      private final static Bit read = Bit.ONE;
 +
 +      private ReadWriteEnd data;
 +      private ReadEnd rWBit, address, clock;
 +
 +      /**
 +       * @param data    The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
 +       *                a memory word
 +       * @param rWBit   The value of the 0th bit dictates the mode: 0: Write, 1: Read
 +       * @param address The bits of this ReadEnd address the memory cell to read/write
 +       */
 +      public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
 +                      ReadEnd rWBit, ReadEnd address, ReadEnd clock)
 +      {
 +              super(timeline, processTime);
 +              if(data.width() != definition.getCellWidth())
 +                      throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
 +              if(rWBit.width() != 1)
 +                      throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
 +              if(address.width() != definition.getMemoryAddressBits())
 +                      throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width()));
 +              this.data = data;
 +              this.rWBit = rWBit;
 +              this.address = address;
 +              this.clock = clock;
 +              data.registerObserver(this);
 +              rWBit.registerObserver(this);
 +              address.registerObserver(this);
 +              clock.registerObserver(this);
 +              
 +              memory = new WordAddressableMemory(definition);
 +      }
 +
 +      @Override
-                       return;
++      protected TimelineEventHandler compute()
 +      {
 +              if(clock.getValue() != Bit.ONE)
-                               data.feedSignals(Bit.U.toVector(data.width()));
-                       else
-                               data.clearSignals();
-                       return;
++                      return null;
++              
 +              if (!address.hasNumericValue())
 +              {
 +                      if (read.equals(rWBit.getValue()))
-                       data.feedSignals(memory.getCell(addressed));
++                              return e -> data.feedSignals(Bit.U.toVector(data.width()));
++                      return e -> data.clearSignals();
 +              }
 +              long addressed = address.getUnsignedValue();
 +              if (read.equals(rWBit.getValue()))
-                       data.clearSignals();
-                       memory.setCell(addressed, data.getValues());
++              {
++                      BitVector storedData = memory.getCell(addressed);
++                      return e -> data.feedSignals(storedData);
++              }
 +              else
 +              {
++                      BitVector transData = data.getValues();
++                      return e ->
++                      {
++                              data.clearSignals();
++                              memory.setCell(addressed, transData);
++                      };
 +              }
 +      }
 +
 +      @Override
 +      public List<ReadEnd> getAllInputs()
 +      {
 +              return List.of(data, rWBit, address);
 +      }
 +
 +      @Override
 +      public List<ReadWriteEnd> getAllOutputs()
 +      {
 +              return List.of(data);
 +      }
 +}
@@@ -20,8 -19,8 +19,8 @@@ import net.mograsim.machine.MainMemoryD
  public class ModelMemoryWA extends ModelComponent
  {
        private final MainMemoryDefinition              definition;
 -      private final Pin                                               addrPin, dataPin, rWPin;
 -      private WordAddressableMemoryComponent  memory;
 +      private final Pin                                               addrPin, dataPin, rWPin, clock;
-       private CoreWordAddressableMemory       memory;
++      private CoreWordAddressableMemory               memory;
        private final static int                                width   = 100, height = 300;
        private Renderer                                                symbolRenderer;
        private Renderer                                                outlineRenderer;