--- /dev/null
+package net.mograsim.machine.standard.memory;
+
+import java.util.List;
+
+import net.mograsim.logic.core.components.BasicCoreComponent;
+import net.mograsim.logic.core.timeline.Timeline;
+import net.mograsim.logic.core.types.Bit;
+import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
+import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
+import net.mograsim.machine.MainMemoryDefinition;
+
+/**
+ * A memory component that only allows access to words of a specific width
+ */
+public class CoreWordAddressableMemory extends BasicCoreComponent
+{
+ private final WordAddressableMemory memory;
+ private final static Bit read = Bit.ONE;
+
+ private ReadWriteEnd data;
+ private ReadEnd rWBit, address, clock;
+
+ /**
+ * @param data The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
+ * a memory word
+ * @param rWBit The value of the 0th bit dictates the mode: 0: Write, 1: Read
+ * @param address The bits of this ReadEnd address the memory cell to read/write
+ */
+ public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
+ ReadEnd rWBit, ReadEnd address, ReadEnd clock)
+ {
+ super(timeline, processTime);
+ if(data.width() != definition.getCellWidth())
+ throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
+ if(rWBit.width() != 1)
+ throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
+ if(address.width() != definition.getMemoryAddressBits())
+ throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width()));
+ this.data = data;
+ this.rWBit = rWBit;
+ this.address = address;
+ this.clock = clock;
+ data.registerObserver(this);
+ rWBit.registerObserver(this);
+ address.registerObserver(this);
+ clock.registerObserver(this);
+
+ memory = new WordAddressableMemory(definition);
+ }
+
+ @Override
+ protected void compute()
+ {
+ if(clock.getValue() != Bit.ONE)
+ return;
+ if (!address.hasNumericValue())
+ {
+ if (read.equals(rWBit.getValue()))
+ data.feedSignals(Bit.U.toVector(data.width()));
+ else
+ data.clearSignals();
+ return;
+ }
+ long addressed = address.getUnsignedValue();
+ if (read.equals(rWBit.getValue()))
+ data.feedSignals(memory.getCell(addressed));
+ else
+ {
+ data.clearSignals();
+ memory.setCell(addressed, data.getValues());
+ }
+ }
+
+ @Override
+ public List<ReadEnd> getAllInputs()
+ {
+ return List.of(data, rWBit, address);
+ }
+
+ @Override
+ public List<ReadWriteEnd> getAllOutputs()
+ {
+ return List.of(data);
+ }
+}
\ No newline at end of file
public class ModelMemoryWA extends ModelComponent
{
private final MainMemoryDefinition definition;
- private final Pin addrPin, dataPin, rWPin;
- private WordAddressableMemoryComponent memory;
+ private final Pin addrPin, dataPin, rWPin, clock;
+ private CoreWordAddressableMemory memory;
private final static int width = 100, height = 300;
private Renderer symbolRenderer;
private Renderer outlineRenderer;
addPin(addrPin = new Pin(model, this, "A", definition.getMemoryAddressBits(), PinUsage.INPUT, 0, 10));
addPin(dataPin = new Pin(model, this, "D", definition.getCellWidth(), PinUsage.TRISTATE, 0, 30));
addPin(rWPin = new Pin(model, this, "RW", 1, PinUsage.INPUT, 0, 50));
+ addPin(clock = new Pin(model, this, "C", 1, PinUsage.INPUT, 0, 70));
init();
}
{
return rWPin;
}
+
+ public Pin getClockPin()
+ {
+ return clock;
+ }
- public void setCoreModelBinding(WordAddressableMemoryComponent memory)
+ public void setCoreModelBinding(CoreWordAddressableMemory memory)
{
this.memory = memory;
}
return definition;
}
- public WordAddressableMemoryComponent getMemory()
+ public CoreWordAddressableMemory getMemory()
{
return memory;
}
return ModelMemoryWA.class;
}
- @SuppressWarnings("unused")
@Override
public void createAndLinkComponent(Timeline timeline, CoreModelParameters params, ModelMemoryWA modelComponent,
Map<Pin, CoreWire> logicWiresPerPin)
ReadWriteEnd data = logicWiresPerPin.get(modelComponent.getDataPin()).createReadWriteEnd();
ReadEnd address = logicWiresPerPin.get(modelComponent.getAddressPin()).createReadOnlyEnd();
ReadEnd mode = logicWiresPerPin.get(modelComponent.getReadWritePin()).createReadOnlyEnd();
- WordAddressableMemoryComponent mem = new WordAddressableMemoryComponent(timeline, 2, modelComponent.getDefinition(), data, mode, address);
+ ReadEnd clock = logicWiresPerPin.get(modelComponent.getClockPin()).createReadOnlyEnd();
+ CoreWordAddressableMemory mem = new CoreWordAddressableMemory(timeline, 2, modelComponent.getDefinition(), data, mode, address, clock);
modelComponent.setCoreModelBinding(mem);
}
+++ /dev/null
-package net.mograsim.machine.standard.memory;
-
-import java.util.List;
-
-import net.mograsim.logic.core.components.BasicCoreComponent;
-import net.mograsim.logic.core.timeline.Timeline;
-import net.mograsim.logic.core.types.Bit;
-import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
-import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
-import net.mograsim.machine.MainMemoryDefinition;
-
-/**
- * A memory component that only allows access to words of a specific width
- */
-public class WordAddressableMemoryComponent extends BasicCoreComponent
-{
- private final WordAddressableMemory memory;
- private final static Bit read = Bit.ONE;
-
- private ReadWriteEnd data;
- private ReadEnd rWBit, address;
-
- /**
- * @param data The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
- * a memory word
- * @param rWBit The value of the 0th bit dictates the mode: 0: Write, 1: Read
- * @param address The bits of this ReadEnd address the memory cell to read/write
- */
- public WordAddressableMemoryComponent(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
- ReadEnd rWBit, ReadEnd address)
- {
- super(timeline, processTime);
- if(data.width() != definition.getCellWidth())
- throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
- if(rWBit.width() != 1)
- throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
- if(address.width() != definition.getMemoryAddressBits())
- throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width()));
- this.data = data;
- this.rWBit = rWBit;
- this.address = address;
- data.registerObserver(this);
- rWBit.registerObserver(this);
- address.registerObserver(this);
-
- memory = new WordAddressableMemory(definition);
- }
-
- @Override
- protected void compute()
- {
- if (!address.hasNumericValue())
- {
- if (read.equals(rWBit.getValue()))
- data.feedSignals(Bit.U.toVector(data.width()));
- else
- data.clearSignals();
- return;
- }
- long addressed = address.getUnsignedValue();
- if (read.equals(rWBit.getValue()))
- data.feedSignals(memory.getCell(addressed));
- else
- {
- data.clearSignals();
- memory.setCell(addressed, data.getValues());
- }
- }
-
- @Override
- public List<ReadEnd> getAllInputs()
- {
- return List.of(data, rWBit, address);
- }
-
- @Override
- public List<ReadWriteEnd> getAllOutputs()
- {
- return List.of(data);
- }
-}
\ No newline at end of file
CoreWire rW = new CoreWire(t, 1, 2);
CoreWire data = new CoreWire(t, 16, 2);
CoreWire address = new CoreWire(t, 64, 2);
+ CoreWire clock = new CoreWire(t, 1, 2);
ReadWriteEnd rWI = rW.createReadWriteEnd();
ReadWriteEnd dataI = data.createReadWriteEnd();
ReadWriteEnd addressI = address.createReadWriteEnd();
+ ReadWriteEnd clockI = clock.createReadWriteEnd();
@SuppressWarnings("unused")
- WordAddressableMemoryComponent memory = new WordAddressableMemoryComponent(t, 4, MainMemoryDefinition.create(64, 16, 4096L, Long.MAX_VALUE), data.createReadWriteEnd(),
- rW.createReadOnlyEnd(), address.createReadOnlyEnd());
+ CoreWordAddressableMemory memory = new CoreWordAddressableMemory(t, 4, MainMemoryDefinition.create(64, 16, 4096L, Long.MAX_VALUE), data.createReadWriteEnd(),
+ rW.createReadOnlyEnd(), address.createReadOnlyEnd(), clock.createReadOnlyEnd());
+ clockI.feedSignals(Bit.ONE);
+
Random r = new Random();
for (long j = 1; j > 0; j *= 2)
{
projects / Mograsim.git / commitdiff