net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java

   1 package net.mograsim.machine.standard.memory;
   2
   3 import java.util.List;
   4
   5 import net.mograsim.logic.core.components.BasicCoreComponent;
   6 import net.mograsim.logic.core.timeline.Timeline;
   7 import net.mograsim.logic.core.types.Bit;
   8 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
   9 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
  10 import net.mograsim.machine.MainMemoryDefinition;
  11
  12 /**
  13  * A memory component that only allows access to words of a specific width
  14  */
  15 public class WordAddressableMemoryComponent extends BasicCoreComponent
  16 {
  17         private final WordAddressableMemory memory;
  18         private final static Bit read = Bit.ONE;
  19
  20         private ReadWriteEnd data;
  21         private ReadEnd rWBit, address;
  22
  23         /**
  24          * @param data    The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
  25          *                a memory word
  26          * @param rWBit   The value of the 0th bit dictates the mode: 0: Write, 1: Read
  27          * @param address The bits of this ReadEnd address the memory cell to read/write
  28          */
  29         public WordAddressableMemoryComponent(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
  30                         ReadEnd rWBit, ReadEnd address)
  31         {
  32                 super(timeline, processTime);
  33                 if(data.width() != definition.getCellWidth())
  34                         throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
  35                 if(rWBit.width() != 1)
  36                         throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
  37                 if(address.width() != definition.getMemoryAddressBits())
  38                         throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width()));
  39                 this.data = data;
  40                 this.rWBit = rWBit;
  41                 this.address = address;
  42                 data.registerObserver(this);
  43                 rWBit.registerObserver(this);
  44                 address.registerObserver(this);
  45
  46                 memory = new WordAddressableMemory(definition);
  47         }
  48
  49         @Override
  50         protected void compute()
  51         {
  52                 if (!address.hasNumericValue())
  53                 {
  54                         if (read.equals(rWBit.getValue()))
  55                                 data.feedSignals(Bit.U.toVector(data.width()));
  56                         else
  57                                 data.clearSignals();
  58                         return;
  59                 }
  60                 long addressed = address.getUnsignedValue();
  61                 if (read.equals(rWBit.getValue()))
  62                         data.feedSignals(memory.getCell(addressed));
  63                 else
  64                 {
  65                         data.clearSignals();
  66                         memory.setCell(addressed, data.getValues());
  67                 }
  68         }
  69
  70         @Override
  71         public List<ReadEnd> getAllInputs()
  72         {
  73                 return List.of(data, rWBit, address);
  74         }
  75
  76         @Override
  77         public List<ReadWriteEnd> getAllOutputs()
  78         {
  79                 return List.of(data);
  80         }
  81 }