Fixed a bug regarding signal widths

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
index f80f808..0e8669a 100644 (file)
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
@@ -10,6 +10,6 @@ public class Input extends IOPort
        @Override
        public String toDeclarationVerilogCode()
        {
-               return "input [" + getWidth() + ":0] " + getName();
+               return "input [" + (getWidth() - 1) + ":0] " + getName();
        }
 }

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java
index 0cea00b..4068d27 100644 (file)
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java
@@ -10,6 +10,6 @@ public class Output extends IOPort
        @Override
        public String toDeclarationVerilogCode()
        {
-               return "output [" + getWidth() + ":0] " + getName();
+               return "output [" + (getWidth() - 1) + ":0] " + getName();
        }
 }

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java
index 10e2a50..7e0f2cc 100644 (file)
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java
@@ -9,6 +9,6 @@ public class Wire extends Signal
 
        public String toDeclarationVerilogCode()
        {
-               return "wire [" + getWidth() + ":0] " + getName() + ";";
+               return "wire [" + (getWidth() - 1) + ":0] " + getName() + ";";
        }
 }