Fixed a bug regarding signal widths
authorDaniel Kirschten <daniel.kirschten@gmx.de>
Sun, 13 Dec 2020 20:37:23 +0000 (21:37 +0100)
committerDaniel Kirschten <daniel.kirschten@gmx.de>
Thu, 14 Jan 2021 14:44:03 +0000 (15:44 +0100)
commit9d37526a97dbec5434e7a2a0d7fcbf02e91a39a2
treeac5c4fd6d38f5811b7b6c9099bab5b7e97d84e11
parenta9a26cf61f9d5cc57657f17a6583fc46b5d8282f
Fixed a bug regarding signal widths
plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java
plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java