VerilogExporter: Components are now named

diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
index e5c2443..70907f1 100644 (file)
--- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
+++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
@@ -423,6 +423,9 @@ public class VerilogExporter
                        result.append(COMPONENT_PREFIX);
                        String paramsString = subcomponentParams.params == JsonNull.INSTANCE ? "" : subcomponentParams.params.toString();
                        result.append(sanitizeVerilog(subcomponentID + paramsString));
+                       result.append(' ');
+                       // abuse the pinIdentifierGenerator for making these unique
+                       result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName));
                        result.append(" (");
                        for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
                        {