import net.mograsim.logic.core.components.CoreClock;
import net.mograsim.logic.core.timeline.Timeline;
import net.mograsim.logic.core.types.BitVector;
-import net.mograsim.machine.mi.MicroInstructionMemory;
import net.mograsim.logic.model.model.LogicModel;
+import net.mograsim.machine.mi.AssignableMicroInstructionMemory;
public interface Machine
{
MainMemory getMainMemory();
- MicroInstructionMemory getMicroInstructionMemory();
+ AssignableMicroInstructionMemory getMicroInstructionMemory();
}