import java.util.List;
-import net.mograsim.logic.core.components.BasicComponent;
+import net.mograsim.logic.core.components.BasicCoreComponent;
import net.mograsim.logic.core.timeline.Timeline;
+import net.mograsim.logic.core.timeline.TimelineEventHandler;
import net.mograsim.logic.core.types.Bit;
import net.mograsim.logic.core.types.BitVector;
-import net.mograsim.logic.core.wires.Wire.ReadEnd;
-import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
+import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
+import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
import net.mograsim.machine.MainMemoryDefinition;
/**
- * A memory component that only allows access to words of a specific length
+ * A memory component that only allows access to words of a specific width
*/
-public class WordAddressableMemoryComponent extends BasicComponent
+public class WordAddressableMemoryComponent extends BasicCoreComponent
{
private final WordAddressableMemory memory;
private final static Bit read = Bit.ONE;
ReadEnd rWBit, ReadEnd address)
{
super(timeline, processTime);
- if(data.length() != definition.getCellWidth())
- throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.length()));
- if(rWBit.length() != 1)
- throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.length()));
- if(address.length() != definition.getMemoryAddressBits())
- throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.length()));
+ if(data.width() != definition.getCellWidth())
+ throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
+ if(rWBit.width() != 1)
+ throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
+ if(address.width() != definition.getMemoryAddressBits())
+ throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width()));
this.data = data;
this.rWBit = rWBit;
this.address = address;
}
@Override
- protected void compute()
+ protected TimelineEventHandler compute()
{
if (!address.hasNumericValue())
{
if (read.equals(rWBit.getValue()))
- data.feedSignals(BitVector.of(Bit.U, data.length()));
- else
- data.clearSignals();
- return;
+ return e -> data.feedSignals(Bit.U.toVector(data.width()));
+ return e -> data.clearSignals();
}
long addressed = address.getUnsignedValue();
if (read.equals(rWBit.getValue()))
- data.feedSignals(memory.getCell(addressed));
+ {
+ BitVector storedData = memory.getCell(addressed);
+ return e -> data.feedSignals(storedData);
+ }
else
{
- data.clearSignals();
- memory.setCell(addressed, data.getValues());
+ BitVector transData = data.getValues();
+ return e ->
+ {
+ data.clearSignals();
+ memory.setCell(addressed, transData);
+ };
}
}