Daniel Kirschten [Sun, 15 Sep 2019 16:19:21 +0000 (18:19 +0200)]
Corrected Am2900MicroInstructionDefinition
Daniel Kirschten [Sun, 15 Sep 2019 16:16:45 +0000 (18:16 +0200)]
A MicroInstructionDefinition now has a default
Daniel Kirschten [Sun, 15 Sep 2019 16:15:06 +0000 (18:15 +0200)]
Removed old and incorrect CoreWire#get(Un)SignedValue
Daniel Kirschten [Sun, 15 Sep 2019 16:00:16 +0000 (18:00 +0200)]
Setting a memory cell no longer causes an infinite loop
Daniel Kirschten [Sun, 15 Sep 2019 14:05:58 +0000 (16:05 +0200)]
Renamed dff80#0 so it can be found easier in HighLevelStateDebugShell
Daniel Kirschten [Sun, 15 Sep 2019 13:52:29 +0000 (15:52 +0200)]
Fixed InstructionView containing every column twice
Daniel Kirschten [Sun, 15 Sep 2019 13:46:03 +0000 (15:46 +0200)]
Fixed a bug causing CoreMemories using their own memories
Daniel Kirschten [Sun, 15 Sep 2019 13:42:31 +0000 (15:42 +0200)]
Fixed two problems causing memory updates to get "missed" by observers
Daniel Kirschten [Sun, 15 Sep 2019 13:11:15 +0000 (15:11 +0200)]
Fixed some bugs preventing Am2900 from working in Eclipse
Daniel Kirschten [Sun, 15 Sep 2019 13:10:32 +0000 (15:10 +0200)]
Incorporated MPM and RAM into Am2900
Daniel Kirschten [Sun, 15 Sep 2019 12:43:39 +0000 (14:43 +0200)]
Fixed a copy-and-paste error
Daniel Kirschten [Sun, 15 Sep 2019 12:33:31 +0000 (14:33 +0200)]
Applied formatter to all source files
Daniel Kirschten [Sun, 15 Sep 2019 12:32:44 +0000 (14:32 +0200)]
Apply formatter, optional problems, save actions to machine project
Daniel Kirschten [Sun, 15 Sep 2019 12:27:15 +0000 (14:27 +0200)]
Made Memories look more like other components
Daniel Kirschten [Sun, 15 Sep 2019 12:12:32 +0000 (14:12 +0200)]
Removed unneccessary clock input for memory components
Daniel Kirschten [Sun, 15 Sep 2019 11:39:53 +0000 (13:39 +0200)]
Renamed some methods and parameters for clarity; removed debug code
Fabian Stemmler [Sun, 15 Sep 2019 11:10:22 +0000 (13:10 +0200)]
Merge branch 'development' of
https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into
development
Conflicts:
net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/standardComponentIDMapping.json
Christian Femers [Sun, 15 Sep 2019 00:11:25 +0000 (02:11 +0200)]
Used SerializableJojo to make standard component id mapping valid JSON
Christian Femers [Sun, 15 Sep 2019 00:08:36 +0000 (02:08 +0200)]
Marked broken Am2901Testbench deprecated, because interface pins changed
Fabian Stemmler [Sun, 15 Sep 2019 00:01:39 +0000 (02:01 +0200)]
Added Am2900 MainMemory and MicroInstructionMemory Core/Model Components
Fabian Stemmler [Sat, 14 Sep 2019 23:59:01 +0000 (01:59 +0200)]
MicroInstructions can now be converted to bits
Fabian Stemmler [Sat, 14 Sep 2019 23:57:44 +0000 (01:57 +0200)]
Fleshed out LazyTableViewer; Rows can now be highlighted
Christian Femers [Sat, 14 Sep 2019 22:28:09 +0000 (00:28 +0200)]
Added methods to LogicModel for easy Component/Wire retrieval.
Daniel Kirschten [Sat, 14 Sep 2019 14:13:35 +0000 (16:13 +0200)]
Am2900: Fixed some inverted signals; made the clock user-controllable
Daniel Kirschten [Sat, 14 Sep 2019 14:11:33 +0000 (16:11 +0200)]
Fixed problems found by ReserializeAndVerifyJSONs
Daniel Kirschten [Sat, 14 Sep 2019 14:11:04 +0000 (16:11 +0200)]
ReserializeAndVerifyJSONs now checks for redundant wires
Daniel Kirschten [Sat, 14 Sep 2019 13:53:45 +0000 (15:53 +0200)]
ReserializeAndVerifyJSONs now checks wire part orientations
Fabian Stemmler [Fri, 13 Sep 2019 15:44:28 +0000 (17:44 +0200)]
Fleshed out Am2900MicroInstructionDefinition
Fabian Stemmler [Fri, 13 Sep 2019 14:16:07 +0000 (16:16 +0200)]
Merge branch 'development' of
https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into
development
Conflicts:
net.mograsim.machine/src/net/mograsim/machine/standard/memory/ModelMemoryWA.java
net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java
Fabian Stemmler [Fri, 13 Sep 2019 14:01:37 +0000 (16:01 +0200)]
Added Clock input to CoreWordAddressableMemory
Daniel Kirschten [Thu, 12 Sep 2019 21:28:38 +0000 (23:28 +0200)]
CoreWire#forceValues didn't notify fused wires
Daniel Kirschten [Thu, 12 Sep 2019 21:25:58 +0000 (23:25 +0200)]
Fixed Am2901 D input bit order
Daniel Kirschten [Thu, 12 Sep 2019 21:13:01 +0000 (23:13 +0200)]
Merge 'transportdelay' into development
Daniel Kirschten [Thu, 12 Sep 2019 21:12:48 +0000 (23:12 +0200)]
Fixed TestableAm2901Impl
Daniel Kirschten [Thu, 12 Sep 2019 20:45:49 +0000 (22:45 +0200)]
Layouted Am2900; fixed small layout problems in some JSONs
Daniel Kirschten [Thu, 12 Sep 2019 19:31:40 +0000 (21:31 +0200)]
Made ModelMemoryWA referencable from components
Daniel Kirschten [Thu, 12 Sep 2019 13:01:26 +0000 (15:01 +0200)]
Added a missing BitDisplay
Daniel Kirschten [Thu, 12 Sep 2019 12:45:36 +0000 (14:45 +0200)]
More work in Am2900:
-created some missing connections
-created switches/displays for things we can't connect yet
Daniel Kirschten [Thu, 12 Sep 2019 12:43:44 +0000 (14:43 +0200)]
Created dff16
Daniel Kirschten [Thu, 12 Sep 2019 12:25:22 +0000 (14:25 +0200)]
Unified D-input of the Am2901; fixed Y input bit order
Daniel Kirschten [Thu, 12 Sep 2019 12:17:01 +0000 (14:17 +0200)]
Continued wiring up Am2900.
It is almost complete now! Missing:
-MPS (or MPM in English?)
-MPROM
-RAM
-some clock signals
(not yet done because I don't know the polarities for some components)
-some Am2901 signals
-HighLevelStates
-layouting, as always
Fabian Stemmler [Thu, 12 Sep 2019 12:10:48 +0000 (14:10 +0200)]
Merge branch 'development' of https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into development
Fabian Stemmler [Thu, 12 Sep 2019 12:04:24 +0000 (14:04 +0200)]
Unified Am2901 I- and Y-inputs
Daniel Kirschten [Thu, 12 Sep 2019 11:37:12 +0000 (13:37 +0200)]
Connected some microinstruction bits to the machine
Daniel Kirschten [Thu, 12 Sep 2019 10:38:01 +0000 (12:38 +0200)]
Added am2901 package to MANIFEST's Export-Packages
Daniel Kirschten [Thu, 12 Sep 2019 10:32:39 +0000 (12:32 +0200)]
Added simple line counter to be able to show off and feel great ;)
Daniel Kirschten [Thu, 12 Sep 2019 10:18:49 +0000 (12:18 +0200)]
dff80 now has HighLevelStates:
"q" all 80 bit (as a BitVector)
"q1"-"q80" single bits (MSBit=q80, LSBit=q1; as Bit or BitVector)
"q8-1"-"q80-73" sub-bytes (MSB=q80-73, LSB=q8-1; as BitVector)
Fabian Stemmler [Thu, 12 Sep 2019 10:18:23 +0000 (12:18 +0200)]
Am2901 finally snaps correctly
Daniel Kirschten [Thu, 12 Sep 2019 09:43:50 +0000 (11:43 +0200)]
Replaced HighLevelStateHandlerContext with SubmodelComponent
Daniel Kirschten [Thu, 12 Sep 2019 09:43:23 +0000 (11:43 +0200)]
Changed sub-DFF names order in dff80
Daniel Kirschten [Thu, 12 Sep 2019 09:21:37 +0000 (11:21 +0200)]
Simple...HardcodedModelComponent now has a constructor without callInit
Daniel Kirschten [Thu, 12 Sep 2019 09:18:22 +0000 (11:18 +0200)]
Added microinstruction register
Daniel Kirschten [Thu, 12 Sep 2019 09:15:18 +0000 (11:15 +0200)]
Created dff8, dff80, mux1_8; reserialized dff12_we, Am2904Testbench
Daniel Kirschten [Thu, 12 Sep 2019 09:12:45 +0000 (11:12 +0200)]
Better exception in DelegatingAtomicHighLevelStateHandler
Daniel Kirschten [Thu, 12 Sep 2019 09:12:18 +0000 (11:12 +0200)]
Removed legacy getIdentifier method; Editor now can duplicate Mergers
Daniel Kirschten [Wed, 11 Sep 2019 16:54:01 +0000 (18:54 +0200)]
dff12_we, dff16_invwe, dff16_we now have HighLevelStates
Daniel Kirschten [Wed, 11 Sep 2019 16:46:50 +0000 (18:46 +0200)]
Changed BitVectorSplittingAtomicHighLevelStateHandler's part order
Daniel Kirschten [Wed, 11 Sep 2019 16:26:54 +0000 (18:26 +0200)]
HighLevelStates are now sorted in JSONs
Daniel Kirschten [Wed, 11 Sep 2019 16:16:43 +0000 (18:16 +0200)]
Editor now draws component names
Daniel Kirschten [Wed, 11 Sep 2019 15:22:51 +0000 (17:22 +0200)]
Improved some snippets (HighLevelStateHandlers and PinNamesRenderer)
Fabian Stemmler [Wed, 11 Sep 2019 15:11:45 +0000 (17:11 +0200)]
Merge branch 'development' of https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into development
Fabian Stemmler [Wed, 11 Sep 2019 15:11:25 +0000 (17:11 +0200)]
Moved a few outputs of Am2901
Daniel Kirschten [Wed, 11 Sep 2019 14:50:17 +0000 (16:50 +0200)]
ReserializeJSONs checks component sizes
Daniel Kirschten [Wed, 11 Sep 2019 14:47:57 +0000 (16:47 +0200)]
Renamed ReserializeJSONs
Daniel Kirschten [Wed, 11 Sep 2019 14:40:47 +0000 (16:40 +0200)]
Made GUIMerger and GUISplitter the same thing
Daniel Kirschten [Wed, 11 Sep 2019 13:43:02 +0000 (15:43 +0200)]
Changed BZ to 16 bit
Daniel Kirschten [Wed, 11 Sep 2019 13:32:38 +0000 (15:32 +0200)]
Fixed a bug causing submodelInterfacePins to "be" in the wrong model
Daniel Kirschten [Wed, 11 Sep 2019 13:16:16 +0000 (15:16 +0200)]
Made Modelinc12 generic
Fabian Stemmler [Tue, 10 Sep 2019 16:13:13 +0000 (18:13 +0200)]
Fleshed out Am2900MicroInstructionDefinition
Fabian Stemmler [Tue, 10 Sep 2019 16:00:16 +0000 (18:00 +0200)]
Fixed a Wire overlapping with a component in Am2901
Fabian Stemmler [Tue, 10 Sep 2019 15:41:55 +0000 (17:41 +0200)]
Fixed crooked Wires and swapped I3 and I4 in Am901ALUInclSource...
Fabian Stemmler [Tue, 10 Sep 2019 15:26:45 +0000 (17:26 +0200)]
Fixed crooked wires
Fabian Stemmler [Tue, 10 Sep 2019 14:40:57 +0000 (16:40 +0200)]
Restructured Am2901 and Am901ALUInclSourceDecodeInclFunctionDecode
Daniel Kirschten [Mon, 9 Sep 2019 15:54:06 +0000 (17:54 +0200)]
Am2900 project: Added components source folder to build.properties
Fabian Stemmler [Mon, 9 Sep 2019 16:02:43 +0000 (18:02 +0200)]
Timeline PriorityQueue now uses stable sorting
Fabian Stemmler [Mon, 9 Sep 2019 15:30:17 +0000 (17:30 +0200)]
Merge branch 'development' of https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into development
Fabian Stemmler [Mon, 9 Sep 2019 15:30:00 +0000 (17:30 +0200)]
Improved Am2900MicroInstructionDefinition
Fabian Stemmler [Mon, 9 Sep 2019 15:29:19 +0000 (17:29 +0200)]
Fixed performance issue with tables
Daniel Kirschten [Mon, 9 Sep 2019 15:28:30 +0000 (17:28 +0200)]
Added net.mograsim.machine to feature
Fabian Stemmler [Mon, 9 Sep 2019 08:53:21 +0000 (10:53 +0200)]
Fixed an issue: InstructionView now updates when immediates are modified
Daniel Kirschten [Sun, 8 Sep 2019 21:55:02 +0000 (23:55 +0200)]
Fixed a layout problem in Am2904
Daniel Kirschten [Sun, 8 Sep 2019 21:35:40 +0000 (23:35 +0200)]
Further work in JSONs:
-layouted Am2904
-ReserializeJSONsSettingUsages now can snap WCPs properly and reports
all components, wire points, and interface pins not snapped to grid
-relayouted Am2910 a bit
-deleted obsolete mux2_4
Daniel Kirschten [Sun, 8 Sep 2019 20:18:25 +0000 (22:18 +0200)]
JsonHandler now supports Unicode (used in Am2904muSR)
Daniel Kirschten [Sun, 8 Sep 2019 15:45:58 +0000 (17:45 +0200)]
Made Am2900 a standard component; HLSShell no longer opens per default
Daniel Kirschten [Sun, 8 Sep 2019 15:43:06 +0000 (17:43 +0200)]
Started layouting the Am2904
Fabian Stemmler [Sun, 8 Sep 2019 14:21:39 +0000 (16:21 +0200)]
CoreComponents now have a transport delay
There is now an issue with simultaneous signal changes, because the
generated events might not be executed in the order in which they are
created.
Daniel Kirschten [Sun, 8 Sep 2019 11:54:30 +0000 (13:54 +0200)]
Changed two component's center texts
Daniel Kirschten [Sun, 8 Sep 2019 11:38:16 +0000 (13:38 +0200)]
Fixed a problem with ModelComponent's names
Daniel Kirschten [Sun, 8 Sep 2019 11:37:45 +0000 (13:37 +0200)]
Fixed Am2904 tests; updated to new SWTHelper version
Daniel Kirschten [Sun, 8 Sep 2019 10:07:56 +0000 (12:07 +0200)]
Redo reserializing components since the problem doesn't lie there
Fabian Stemmler [Sat, 7 Sep 2019 14:06:16 +0000 (16:06 +0200)]
Added address column to instruction editor
Fabian Stemmler [Fri, 6 Sep 2019 20:13:45 +0000 (22:13 +0200)]
Merge branch 'development' of
https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into
development
Conflicts:
net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/machine/Am2900Machine.java
net.mograsim.machine/src/net/mograsim/machine/Machine.java
Fabian Stemmler [Fri, 6 Sep 2019 19:04:07 +0000 (21:04 +0200)]
Updated Am2900Machine and -Definition; Added MachineContext
MemoryView and InstructionView were updated to depend on the
MachineContext
Daniel Kirschten [Fri, 6 Sep 2019 08:41:30 +0000 (10:41 +0200)]
Undo reserializing components since something broke
Daniel Kirschten [Fri, 6 Sep 2019 07:50:22 +0000 (09:50 +0200)]
Fixed a performance issue in CoreWire introduced when fixing Fusions
Daniel Kirschten [Thu, 5 Sep 2019 22:44:28 +0000 (00:44 +0200)]
Reserialized components with default names
Daniel Kirschten [Thu, 5 Sep 2019 22:43:49 +0000 (00:43 +0200)]
Cleaned up ID overriding in DeserializedSubmodelComponent
Daniel Kirschten [Thu, 5 Sep 2019 22:05:30 +0000 (00:05 +0200)]
Reserialized JSONs (changed component order due to new IDs)
Daniel Kirschten [Thu, 5 Sep 2019 22:03:32 +0000 (00:03 +0200)]
Cleaned LogicModelModifiable.getDefaultComponentName
Daniel Kirschten [Thu, 5 Sep 2019 22:03:16 +0000 (00:03 +0200)]
Repaired Am2904Testbench