Fabian Stemmler [Tue, 17 Sep 2019 20:57:40 +0000 (22:57 +0200)]
WordAddressableMemory will now ignore non-binary BitVectors
Fabian Stemmler [Tue, 17 Sep 2019 19:42:21 +0000 (21:42 +0200)]
Merge branch 'development' of
https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into
development
Conflicts:
plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/machine/Am2900Machine.java
Fabian Stemmler [Tue, 17 Sep 2019 19:40:57 +0000 (21:40 +0200)]
MicroInstructionMemory editor can now open and save to files
Daniel Kirschten [Tue, 17 Sep 2019 16:02:40 +0000 (18:02 +0200)]
Corrected RAM control signal timing
Daniel Kirschten [Tue, 17 Sep 2019 12:31:40 +0000 (14:31 +0200)]
Made Am2900 work again in ModelComponentTestbench
Daniel Kirschten [Tue, 17 Sep 2019 12:25:03 +0000 (14:25 +0200)]
Reserialized components
Fabian Stemmler [Mon, 16 Sep 2019 18:28:24 +0000 (20:28 +0200)]
Removed InstructionView as View
Fabian Stemmler [Mon, 16 Sep 2019 15:56:03 +0000 (17:56 +0200)]
Merge branch 'development' of https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into development
Daniel Kirschten [Mon, 16 Sep 2019 15:52:20 +0000 (17:52 +0200)]
Removed legacy code from ModelSplitter
Daniel Kirschten [Mon, 16 Sep 2019 15:51:29 +0000 (17:51 +0200)]
Removed legacy ModelMerger
Daniel Kirschten [Mon, 16 Sep 2019 15:49:55 +0000 (17:49 +0200)]
Reserialized TestableAm2904
Daniel Kirschten [Mon, 16 Sep 2019 15:48:33 +0000 (17:48 +0200)]
Fixed a javadoc comment in SubmodelComponentSerializer
Daniel Kirschten [Mon, 16 Sep 2019 15:48:16 +0000 (17:48 +0200)]
Removed legacy version line handling from JsonHandler for speedup
Daniel Kirschten [Mon, 16 Sep 2019 15:47:54 +0000 (17:47 +0200)]
Made IndirectModelComponentCreator a bit faster
Daniel Kirschten [Mon, 16 Sep 2019 15:47:47 +0000 (17:47 +0200)]
Removed LegacySubmCompSerializer
Daniel Kirschten [Mon, 16 Sep 2019 15:46:01 +0000 (17:46 +0200)]
Removed overkill version attribute from standardComponentIDMapping
Fabian Stemmler [Mon, 16 Sep 2019 15:44:17 +0000 (17:44 +0200)]
Changed InstructionView into an Editor
Fabian Stemmler [Mon, 16 Sep 2019 15:35:27 +0000 (17:35 +0200)]
Made MicroInstructions immutable
Daniel Kirschten [Mon, 16 Sep 2019 15:23:40 +0000 (17:23 +0200)]
Am2900 now has HighLevelStates
Daniel Kirschten [Mon, 16 Sep 2019 15:23:29 +0000 (17:23 +0200)]
JsonHandler preserves line numbers
Daniel Kirschten [Mon, 16 Sep 2019 14:28:31 +0000 (16:28 +0200)]
Improved preference handling in plugin.core
Daniel Kirschten [Mon, 16 Sep 2019 12:46:02 +0000 (14:46 +0200)]
Introduced some preferences
Daniel Kirschten [Mon, 16 Sep 2019 12:28:58 +0000 (14:28 +0200)]
Renamed net.mograsim.logic.tests to net.mograsim.logic.core.tests
Daniel Kirschten [Mon, 16 Sep 2019 12:23:45 +0000 (14:23 +0200)]
Fixed Clock polarities to values where the Am2900 works
Daniel Kirschten [Mon, 16 Sep 2019 11:49:13 +0000 (13:49 +0200)]
InstructionView now guesses the width of columns better
Daniel Kirschten [Mon, 16 Sep 2019 11:48:51 +0000 (13:48 +0200)]
Fixed Am2900MicroInstructionMemoryDefinition's maximal address
Daniel Kirschten [Mon, 16 Sep 2019 11:32:53 +0000 (13:32 +0200)]
Fixed displayed microinstruction bit order
Daniel Kirschten [Mon, 16 Sep 2019 11:00:17 +0000 (13:00 +0200)]
Fixed a FixedOutput in Am2900
Daniel Kirschten [Mon, 16 Sep 2019 10:46:53 +0000 (12:46 +0200)]
Wrote simple, basic tutorial for building Mograsim from source
Daniel Kirschten [Mon, 16 Sep 2019 08:57:28 +0000 (10:57 +0200)]
Changed SWTHelper submodule name to SWTHelper/bundles
Daniel Kirschten [Mon, 16 Sep 2019 08:16:08 +0000 (10:16 +0200)]
Updated SWTHelper: Maven builds no longer cause changes being displayed
Daniel Kirschten [Mon, 16 Sep 2019 07:52:54 +0000 (09:52 +0200)]
Changed some .project files since Eclipse is very picky
Daniel Kirschten [Mon, 16 Sep 2019 07:22:09 +0000 (09:22 +0200)]
Merge branch 'cont-integr-2' into 'development'
Switch to automatic build and test
See merge request lrr-tum/students/eragp-misim-2019!1
Christian Femers [Mon, 16 Sep 2019 01:15:26 +0000 (03:15 +0200)]
Shortened the memory test a bit because it was longer than necessary
Christian Femers [Mon, 16 Sep 2019 01:14:18 +0000 (03:14 +0200)]
Fixed bug in CoreWordAddressableMemory where signals were not cleared.
Christian Femers [Mon, 16 Sep 2019 00:39:16 +0000 (02:39 +0200)]
Made WordAddressableMemoryTest less random and better at finding errors.
Christian Femers [Mon, 16 Sep 2019 00:19:38 +0000 (02:19 +0200)]
Fixed reference to the old structure in the yaml
Christian Femers [Mon, 16 Sep 2019 00:16:05 +0000 (02:16 +0200)]
The final restructured version for automatic build using maven tycho
This can be extended to automatically deploy the updatesite to e.g. ftp.
The difference to the previous CI approach is the flatter structure of
the project and some pipeline improvements.
Daniel Kirschten [Sun, 15 Sep 2019 19:37:05 +0000 (21:37 +0200)]
Fixed a bug in Am2900; created dlatch8/80; relayouted some components
Daniel Kirschten [Sun, 15 Sep 2019 19:35:49 +0000 (21:35 +0200)]
Fixed an error in Am2900MicroInstructionDefinition
Daniel Kirschten [Sun, 15 Sep 2019 19:35:33 +0000 (21:35 +0200)]
MPM load no longer causes Timeline to crash
Daniel Kirschten [Sun, 15 Sep 2019 19:31:35 +0000 (21:31 +0200)]
Fixed a crashbug in Editor when deleting selections with wires and comps
Daniel Kirschten [Sun, 15 Sep 2019 16:19:21 +0000 (18:19 +0200)]
Corrected Am2900MicroInstructionDefinition
Daniel Kirschten [Sun, 15 Sep 2019 16:16:45 +0000 (18:16 +0200)]
A MicroInstructionDefinition now has a default
Daniel Kirschten [Sun, 15 Sep 2019 16:15:06 +0000 (18:15 +0200)]
Removed old and incorrect CoreWire#get(Un)SignedValue
Daniel Kirschten [Sun, 15 Sep 2019 16:00:16 +0000 (18:00 +0200)]
Setting a memory cell no longer causes an infinite loop
Daniel Kirschten [Sun, 15 Sep 2019 14:05:58 +0000 (16:05 +0200)]
Renamed dff80#0 so it can be found easier in HighLevelStateDebugShell
Daniel Kirschten [Sun, 15 Sep 2019 13:52:29 +0000 (15:52 +0200)]
Fixed InstructionView containing every column twice
Daniel Kirschten [Sun, 15 Sep 2019 13:46:03 +0000 (15:46 +0200)]
Fixed a bug causing CoreMemories using their own memories
Daniel Kirschten [Sun, 15 Sep 2019 13:42:31 +0000 (15:42 +0200)]
Fixed two problems causing memory updates to get "missed" by observers
Daniel Kirschten [Sun, 15 Sep 2019 13:11:15 +0000 (15:11 +0200)]
Fixed some bugs preventing Am2900 from working in Eclipse
Daniel Kirschten [Sun, 15 Sep 2019 13:10:32 +0000 (15:10 +0200)]
Incorporated MPM and RAM into Am2900
Daniel Kirschten [Sun, 15 Sep 2019 12:43:39 +0000 (14:43 +0200)]
Fixed a copy-and-paste error
Daniel Kirschten [Sun, 15 Sep 2019 12:33:31 +0000 (14:33 +0200)]
Applied formatter to all source files
Daniel Kirschten [Sun, 15 Sep 2019 12:32:44 +0000 (14:32 +0200)]
Apply formatter, optional problems, save actions to machine project
Daniel Kirschten [Sun, 15 Sep 2019 12:27:15 +0000 (14:27 +0200)]
Made Memories look more like other components
Daniel Kirschten [Sun, 15 Sep 2019 12:12:32 +0000 (14:12 +0200)]
Removed unneccessary clock input for memory components
Daniel Kirschten [Sun, 15 Sep 2019 11:39:53 +0000 (13:39 +0200)]
Renamed some methods and parameters for clarity; removed debug code
Fabian Stemmler [Sun, 15 Sep 2019 11:10:22 +0000 (13:10 +0200)]
Merge branch 'development' of
https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into
development
Conflicts:
net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/standardComponentIDMapping.json
Christian Femers [Sun, 15 Sep 2019 00:11:25 +0000 (02:11 +0200)]
Used SerializableJojo to make standard component id mapping valid JSON
Christian Femers [Sun, 15 Sep 2019 00:08:36 +0000 (02:08 +0200)]
Marked broken Am2901Testbench deprecated, because interface pins changed
Fabian Stemmler [Sun, 15 Sep 2019 00:01:39 +0000 (02:01 +0200)]
Added Am2900 MainMemory and MicroInstructionMemory Core/Model Components
Fabian Stemmler [Sat, 14 Sep 2019 23:59:01 +0000 (01:59 +0200)]
MicroInstructions can now be converted to bits
Fabian Stemmler [Sat, 14 Sep 2019 23:57:44 +0000 (01:57 +0200)]
Fleshed out LazyTableViewer; Rows can now be highlighted
Christian Femers [Sat, 14 Sep 2019 22:28:09 +0000 (00:28 +0200)]
Added methods to LogicModel for easy Component/Wire retrieval.
Daniel Kirschten [Sat, 14 Sep 2019 14:13:35 +0000 (16:13 +0200)]
Am2900: Fixed some inverted signals; made the clock user-controllable
Daniel Kirschten [Sat, 14 Sep 2019 14:11:33 +0000 (16:11 +0200)]
Fixed problems found by ReserializeAndVerifyJSONs
Daniel Kirschten [Sat, 14 Sep 2019 14:11:04 +0000 (16:11 +0200)]
ReserializeAndVerifyJSONs now checks for redundant wires
Daniel Kirschten [Sat, 14 Sep 2019 13:53:45 +0000 (15:53 +0200)]
ReserializeAndVerifyJSONs now checks wire part orientations
Fabian Stemmler [Fri, 13 Sep 2019 15:44:28 +0000 (17:44 +0200)]
Fleshed out Am2900MicroInstructionDefinition
Fabian Stemmler [Fri, 13 Sep 2019 14:16:07 +0000 (16:16 +0200)]
Merge branch 'development' of
https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into
development
Conflicts:
net.mograsim.machine/src/net/mograsim/machine/standard/memory/ModelMemoryWA.java
net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java
Fabian Stemmler [Fri, 13 Sep 2019 14:01:37 +0000 (16:01 +0200)]
Added Clock input to CoreWordAddressableMemory
Daniel Kirschten [Thu, 12 Sep 2019 21:28:38 +0000 (23:28 +0200)]
CoreWire#forceValues didn't notify fused wires
Daniel Kirschten [Thu, 12 Sep 2019 21:25:58 +0000 (23:25 +0200)]
Fixed Am2901 D input bit order
Daniel Kirschten [Thu, 12 Sep 2019 21:13:01 +0000 (23:13 +0200)]
Merge 'transportdelay' into development
Daniel Kirschten [Thu, 12 Sep 2019 21:12:48 +0000 (23:12 +0200)]
Fixed TestableAm2901Impl
Daniel Kirschten [Thu, 12 Sep 2019 20:45:49 +0000 (22:45 +0200)]
Layouted Am2900; fixed small layout problems in some JSONs
Daniel Kirschten [Thu, 12 Sep 2019 19:31:40 +0000 (21:31 +0200)]
Made ModelMemoryWA referencable from components
Daniel Kirschten [Thu, 12 Sep 2019 13:01:26 +0000 (15:01 +0200)]
Added a missing BitDisplay
Daniel Kirschten [Thu, 12 Sep 2019 12:45:36 +0000 (14:45 +0200)]
More work in Am2900:
-created some missing connections
-created switches/displays for things we can't connect yet
Daniel Kirschten [Thu, 12 Sep 2019 12:43:44 +0000 (14:43 +0200)]
Created dff16
Daniel Kirschten [Thu, 12 Sep 2019 12:25:22 +0000 (14:25 +0200)]
Unified D-input of the Am2901; fixed Y input bit order
Daniel Kirschten [Thu, 12 Sep 2019 12:17:01 +0000 (14:17 +0200)]
Continued wiring up Am2900.
It is almost complete now! Missing:
-MPS (or MPM in English?)
-MPROM
-RAM
-some clock signals
(not yet done because I don't know the polarities for some components)
-some Am2901 signals
-HighLevelStates
-layouting, as always
Fabian Stemmler [Thu, 12 Sep 2019 12:10:48 +0000 (14:10 +0200)]
Merge branch 'development' of https://gitlab.lrz.de/lrr-tum/students/eragp-misim-2019.git into development
Fabian Stemmler [Thu, 12 Sep 2019 12:04:24 +0000 (14:04 +0200)]
Unified Am2901 I- and Y-inputs
Daniel Kirschten [Thu, 12 Sep 2019 11:37:12 +0000 (13:37 +0200)]
Connected some microinstruction bits to the machine
Daniel Kirschten [Thu, 12 Sep 2019 10:38:01 +0000 (12:38 +0200)]
Added am2901 package to MANIFEST's Export-Packages
Daniel Kirschten [Thu, 12 Sep 2019 10:32:39 +0000 (12:32 +0200)]
Added simple line counter to be able to show off and feel great ;)
Daniel Kirschten [Thu, 12 Sep 2019 10:18:49 +0000 (12:18 +0200)]
dff80 now has HighLevelStates:
"q" all 80 bit (as a BitVector)
"q1"-"q80" single bits (MSBit=q80, LSBit=q1; as Bit or BitVector)
"q8-1"-"q80-73" sub-bytes (MSB=q80-73, LSB=q8-1; as BitVector)
Fabian Stemmler [Thu, 12 Sep 2019 10:18:23 +0000 (12:18 +0200)]
Am2901 finally snaps correctly
Daniel Kirschten [Thu, 12 Sep 2019 09:43:50 +0000 (11:43 +0200)]
Replaced HighLevelStateHandlerContext with SubmodelComponent
Daniel Kirschten [Thu, 12 Sep 2019 09:43:23 +0000 (11:43 +0200)]
Changed sub-DFF names order in dff80
Daniel Kirschten [Thu, 12 Sep 2019 09:21:37 +0000 (11:21 +0200)]
Simple...HardcodedModelComponent now has a constructor without callInit
Daniel Kirschten [Thu, 12 Sep 2019 09:18:22 +0000 (11:18 +0200)]
Added microinstruction register
Daniel Kirschten [Thu, 12 Sep 2019 09:15:18 +0000 (11:15 +0200)]
Created dff8, dff80, mux1_8; reserialized dff12_we, Am2904Testbench
Daniel Kirschten [Thu, 12 Sep 2019 09:12:45 +0000 (11:12 +0200)]
Better exception in DelegatingAtomicHighLevelStateHandler
Daniel Kirschten [Thu, 12 Sep 2019 09:12:18 +0000 (11:12 +0200)]
Removed legacy getIdentifier method; Editor now can duplicate Mergers
Daniel Kirschten [Wed, 11 Sep 2019 16:54:01 +0000 (18:54 +0200)]
dff12_we, dff16_invwe, dff16_we now have HighLevelStates
Daniel Kirschten [Wed, 11 Sep 2019 16:46:50 +0000 (18:46 +0200)]
Changed BitVectorSplittingAtomicHighLevelStateHandler's part order
Daniel Kirschten [Wed, 11 Sep 2019 16:26:54 +0000 (18:26 +0200)]
HighLevelStates are now sorted in JSONs