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Fusing Wires will no longer initialize Wires with value U
2019-06-21 Fabian StemmlerFusing Wires will no longer initialize Wires with value U
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2019-06-21 Fabian StemmlerQuickfix for Wire.fuse(...)
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2019-06-21 Fabian StemmlerUpdated SubmodelComponentParams json format
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2019-06-18 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
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2019-06-18 Fabian StemmlerLogic Wire bits can now be fused together (Wire.fuse...
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2019-06-18 Fabian StemmlerAdded file version and closed resource leak
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2019-06-17 Fabian StemmlerProviding json examples
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2019-06-17 Fabian StemmlerCleaned up GUICustomComponentCreator and wrote documentation.
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2019-06-16 Fabian StemmlerSimplified file representation of SubmodelComponents
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2019-06-14 Fabian StemmlerGeneral SubmodelComponents can now be saved to a json...
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2019-06-10 Fabian StemmlerAdded file representation for SimpleRectangularSubmodelCompo...
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2019-06-08 Fabian StemmlerFixed a refactoring issue in GUIsel2_4
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2019-06-08 Fabian StemmlerAdded GUIsel2_4
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2019-06-05 Fabian StemmlerAdded GUImux1_4.
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2019-06-05 Fabian StemmlerAdded GUImux1.
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2019-06-05 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
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2019-06-05 Fabian StemmlerAdded fulladder. GUIWires are now drawn with right...
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2019-06-05 Fabian StemmlerFixed nand and nor gate to work with more than two...
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2019-06-04 Fabian StemmlerAdded nand and nor gate due to popular demand
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2019-06-02 Fabian StemmlerBitDisplay, ManualSwitch now Observable. More Docs...
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2019-06-02 Fabian StemmlerCleanup; Cleared warnings in the logic core
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2019-06-02 Fabian StemmlerGeneralized WireObserver to LogicObserver
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2019-05-29 Fabian StemmlerMerge branch 'development' of
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2019-05-29 Fabian StemmlerMerge branch 'development' of
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2019-05-29 Fabian StemmlerMerge branch 'development' of
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2019-05-29 Fabian StemmlerTimeline updated (executeUntil, setTimeFunction)
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2019-05-27 Fabian StemmlerTimeline now passed via constructor
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2019-05-25 Fabian StemmlerMade LogicUI compatible with ReadEnd and ReadWriteEnd
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2019-05-24 Fabian StemmlerCompletion of ReadEnd and ReadWriteEnd addition
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2019-05-24 Fabian StemmlerWireEnd functionality split into ReadEnd and ReadWriteEnd
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2019-05-20 Fabian Stemmlernew WireEnds as in/outputs are now initialized with...
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2019-05-20 Fabian StemmlerCleanup
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2019-05-20 Fabian StemmlerMerge logic of origin into logic
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2019-05-20 Fabian StemmlerWireArray(Input) is now Wire(End); all in-/outputs...
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2019-05-18 Fabian StemmlerAdded project specific format; Default values in WireArray...
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2019-05-18 Fabian StemmlerReformatted everything. Eclipse built-in Linewrapping...
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2019-05-13 Fabian Stemmlerlogic gates and, or and xor now take an arbitrary amount...
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2019-05-12 Fabian Stemmleradded demux; added getAllInputs() and getAllOutputs...
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2019-05-12 Fabian Stemmleradded more doc to Timeline; added functionality to Bit
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2019-05-11 Fabian StemmlerCleaned up ComponentTest.
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2019-05-11 Fabian StemmlerRemoved Mapper class.
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2019-05-10 Fabian StemmlerFixed Merger, Mux, Splitter: onedirectional again....
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2019-05-10 Fabian Stemmlerbin deleted and ignored.
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2019-05-10 Fabian StemmlerWire concept was changed to accommodate multiple inputs...
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2019-05-07 Fabian StemmlerAdded era.mi; Project containing provisional simulator...
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2019-05-07 Fabian StemmlerAdded era.mi; Project containing provisional simulator...
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