Mograsim.git
2020-04-12 Daniel KirschtenResurrected the XNOR gate
2020-04-12 Daniel KirschtenMerged LD and _RLD inputs of ModelAm2910RegCntr into...
2020-04-11 Daniel KirschtenRedefined PinUsages; cleaned component JSONs
2020-04-11 Daniel KirschtenFixed ReserializeAndVerifyJSONs.changePinUsages
2020-04-11 Daniel KirschtenAdjusted Am2910 layout to new sel4_12
2020-04-11 Daniel KirschtenImplemented sel4_12 gate-based
2020-04-11 Daniel KirschtenImplemented a 4-bit sel4
2020-04-11 Daniel KirschtenImplemented sel4
2020-04-11 Daniel KirschtenIndirectModelComponentCreator no longer caches jsonfile...
2020-04-09 Daniel KirschtenFixed a layouting bug in Am2910InstrPLA
2020-04-09 Daniel KirschtenSimplified BitVector (de)serializing
2020-04-07 Daniel KirschtenAdjusted Am2910 to new Am2910InstrPLA layout
2020-04-07 Daniel KirschtenRe-layouted the rest of the Am2910InstrPLA
2020-04-07 Daniel KirschtenRe-layouted part of the Am2910InstrPLA
2020-04-02 Daniel KirschtenRe-layouted part of the Am2910InstrPLA
2020-04-01 Daniel KirschtenAdded a GCD test case
2020-03-31 Daniel KirschtenMerge branch 'development' into 'master'
2020-03-31 Daniel KirschtenFixed dff4_finewe HLS bit order
2020-03-31 Daniel KirschtenAdjusted layouts of Am2900 and Am2910
2020-03-31 Daniel KirschtenCreated gate-based implementations of an incrementer...
2020-03-31 Daniel KirschtenCreated a gate-based implementation of dff4_finewe
2020-03-30 Daniel KirschtenAdjusted layout of the Am2910 again
2020-03-30 Daniel KirschtenCreated a gate-based implementation of dff12
2020-03-30 Daniel KirschtenAdjusted layout of the Am2910 (again...)
2020-03-30 Daniel KirschtenCreated a gate-based implementation of nor12
2020-03-30 Daniel KirschtenAdjusted layout of the Am2910
2020-03-30 Daniel KirschtenDeleted old hardcoded Am2910InstrPLA
2020-03-30 Daniel KirschtenInverted the _PL, _MAP, _VECT outputs of the Am2910InstrPLA
2020-03-30 Daniel KirschtenAdded a SymbolRenderer for the Am2910InstrPLA
2020-03-30 Daniel KirschtenImplemented the YF output of the Am2910InstrPLA in...
2020-03-30 Daniel KirschtenImplemented the YR output of the Am2910InstrPLA in...
2020-03-30 Daniel KirschtenImplemented the STKI1 output of the Am2910InstrPLA...
2020-03-27 Daniel KirschtenImplemented the STKI0 output of the Am2910InstrPLA...
2020-03-27 Daniel KirschtenOrganized imports
2020-03-27 Daniel KirschtenRestructured the Preferences system
2020-03-27 Daniel KirschtenFixed an endless redraw loop on GTK
2020-03-26 Daniel KirschtenLayouted the gates for YmuPC in Am2910InstrPLA
2020-03-26 Daniel KirschtenImplemented the YmuPC output of the Am2910InstrPLA...
2020-03-26 Christian FemersUpdate README to use GitHub Actions Build Status
2020-03-26 Daniel KirschtenImplemented the YD output of the Am2910InstrPLA in...
2020-03-26 Daniel KirschtenChanged the line ending to LF in the Resource settings...
2020-03-26 Daniel KirschtenImplemented a part of the Am2910InstrPLA on gate level
2020-03-26 Daniel KirschtenFixed a bug in the ModelAm2910InstrPLA
2020-03-25 Daniel KirschtenReserializeAndVerifyJSONs now uses the unicode escape...
2020-03-25 Daniel KirschtenAm2910: Changed communication between reg and instrdecode
2020-03-25 Daniel KirschtenGrouped some 4 bit wires in the Am2901
2020-03-25 Daniel KirschtenImproved layout of andor414
2020-03-25 Daniel KirschtenMade and41 smaller
2020-03-25 Daniel KirschtenMade the and gate smaller
2020-03-25 Daniel KirschtenBuilt a XNOR gate
2020-03-25 Daniel KirschtenVerilogExporter now orders interface pins more transpar...
2020-03-25 Daniel KirschtenChanged how the SubmodelComponent decides whether to...
2020-03-25 Daniel KirschtenVerilogExporter now "hands through" a clk signal
2020-02-11 Daniel KirschtenMerge pull request #11 from MaisiKoleni/config-gh-actions
2020-02-11 Christian FemersGH-Actions clone submodules
2020-02-11 Christian FemersConfigure GitHub Actions for Mograsim
2020-02-04 Daniel KirschtenGenerated Verilog now has a RST "pin"
2020-02-04 Daniel KirschtenLogicCoreAdapter now makes global statistics for gate...
2020-01-06 Daniel KirschtenModelComponentTestbench's Switches/Displays are named...
2020-01-06 Daniel KirschtenModelComponentTestbench works again
2020-01-05 Daniel KirschtenVerilogExporter: Components are now named
2020-01-05 Daniel KirschtenVerilogExporter: Fixed serializing components without...
2020-01-05 Daniel KirschtenAdded a class for exporting component JSONs to Verilog
2019-11-25 Daniel KirschtenMade ModelAm2904RegCTInstrDecode more robust against...
2019-11-25 Daniel KirschtenImproved JavaJsonLineCounter a bit
2019-11-15 Daniel KirschtenSwitched to using logical U for mnemonic X to avoid...
2019-11-15 Daniel KirschtenChanged mnemonic X to use BitVector X; added X for...
2019-11-13 Daniel KirschtenChanged microinstruction column titles to English
2019-11-13 Daniel KirschtenAdjusted some param titles
2019-11-13 Daniel KirschtenAdded short titles for MPM columns
2019-11-13 Daniel KirschtenAdded possibility to swap column tooltip and title...
2019-11-13 Daniel KirschtenUpdated getting_started.md
2019-10-30 Daniel KirschtenFixed the documentation
2019-10-30 Daniel KirschtenAdded a (very elaborately _cough_) explanation for...
2019-10-30 Daniel KirschtenAdded TestGCD
2019-10-30 Daniel KirschtenMicroInstructionMemoryParser and MainMemoryParser now...
2019-10-30 Daniel KirschtenMade hardcoded components slower to fix a timing bug...
2019-10-30 Daniel KirschtenFixed a timing bug in SimpleRectangularHardcodedModelCo...
2019-10-30 Daniel KirschtenFixed a bug in the Am2900
2019-10-30 Daniel KirschtenAm2900Machine now resets registers in strict mode too
2019-10-24 Christian FemersChanged readme for better status report
2019-10-24 Christian FemersAdded master build status to readme
2019-10-24 Christian Femersadded basic travis ci config for testing it
2019-10-23 Christian FemersFixed description in readme
2019-10-23 Christian FemersSwitched to Maven Tycho 1.5.0
2019-10-17 Christian FemersSmall fixes to mograsim development environment notes.
2019-10-17 Christian FemersAdded new Mograsim project wizard and updated getting...
2019-10-16 Christian FemersRemoved unused code of Bit
2019-10-16 Christian FemersAdded note about GitLab CI artifact
2019-10-16 Christian FemersDeactivated asm editor temporarily
2019-10-16 Christian FemersFixed repository artifact
2019-10-16 Christian FemersTry modified pipeline with repository artifact
2019-10-15 Daniel KirschtenUpdated to new SWTHelper version
2019-10-14 Christian FemersMerge branch 'development' of https://gitlab.lrz.de...
2019-10-14 Christian FemersAutomatically add the default Mograsim memory block...
2019-10-14 Daniel KirschtenFixed a bug when the address size is not divisible...
2019-10-14 Christian FemersMerge branch 'development' of https://gitlab.lrz.de...
2019-10-14 Daniel KirschtenFixed bounds checking and address length in MainMemoryB...
2019-10-14 Christian FemersAllow to add nature and configure in one step
2019-10-14 Christian FemersFixed JavaDoc
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