1 package net.mograsim.logic.model.verilog.model;
3 import java.util.Objects;
7 private final Signal source;
8 private final NamedSignal target;
10 public Assign(Signal source, NamedSignal target)
12 this.source = Objects.requireNonNull(source);
13 this.target = Objects.requireNonNull(target);
20 if (source.getWidth() != target.getWidth())
21 throw new IllegalArgumentException("Signal widthes don't match");
24 public Signal getSource()
29 public Signal getTarget()
34 public String toVerilogCode()
36 return "assign " + target.toReferenceVerilogCode() + " = " + source.toReferenceVerilogCode() + ";";
40 public String toString()
42 return target.getName() + " = " + source.toReferenceVerilogCode();
50 result = prime * result + ((source == null) ? 0 : source.hashCode());
51 result = prime * result + ((target == null) ? 0 : target.hashCode());
56 public boolean equals(Object obj)
62 if (getClass() != obj.getClass())
64 Assign other = (Assign) obj;
67 if (other.source != null)
69 } else if (!source.equals(other.source))
73 if (other.target != null)
75 } else if (!target.equals(other.target))