ModelComponentToVerilogConverter can now convert TriStateBuffers
[Mograsim.git] / plugins / net.mograsim.logic.model.verilog / src / net / mograsim / logic / model / verilog / model / expressions / Expression.java
1 package net.mograsim.logic.model.verilog.model.expressions;
2
3 import java.util.Set;
4
5 import net.mograsim.logic.model.verilog.model.signals.Signal;
6
7 public abstract class Expression
8 {
9         private final int width;
10
11         public Expression(int width)
12         {
13                 this.width = width;
14
15                 check();
16         }
17
18         private void check()
19         {
20                 if (width < 0)
21                         throw new IllegalArgumentException("Width can't be negative");
22         }
23
24         public int getWidth()
25         {
26                 return width;
27         }
28
29         public abstract String toVerilogCode();
30
31         public abstract Set<Signal> getReferencedSignals();
32 }