1 package net.mograsim.machine.standard.memory;
5 import net.mograsim.logic.core.timeline.Timeline;
6 import net.mograsim.logic.core.wires.CoreWire;
7 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
8 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
9 import net.mograsim.logic.model.model.wires.Pin;
10 import net.mograsim.logic.model.modeladapter.CoreModelParameters;
11 import net.mograsim.logic.model.modeladapter.componentadapters.ComponentAdapter;
12 import net.mograsim.machine.BitVectorMemory;
13 import net.mograsim.machine.BitVectorMemoryDefinition;
15 public class BitVectorMemoryAdapter implements ComponentAdapter<AbstractModelBitVectorMemory<?, ?>>
17 @SuppressWarnings({ "cast", "unchecked", "rawtypes" })
19 public Class<AbstractModelBitVectorMemory<?, ?>> getSupportedClass()
21 return (Class<AbstractModelBitVectorMemory<?, ?>>) (Class) AbstractModelBitVectorMemory.class;
25 public void createAndLinkComponent(Timeline timeline, CoreModelParameters params, AbstractModelBitVectorMemory<?, ?> modelComponent,
26 Map<Pin, CoreWire> logicWiresPerPin)
28 createAndLinkComponentCasted(timeline, params, modelComponent, logicWiresPerPin);
31 private static <M extends BitVectorMemory, D extends BitVectorMemoryDefinition> void createAndLinkComponentCasted(Timeline timeline,
32 CoreModelParameters params, AbstractModelBitVectorMemory<M, D> modelComponent, Map<Pin, CoreWire> logicWiresPerPin)
34 ReadWriteEnd data = logicWiresPerPin.get(modelComponent.getDataPin()).createReadWriteEnd();
35 ReadEnd address = logicWiresPerPin.get(modelComponent.getAddressPin()).createReadOnlyEnd();
36 ReadEnd rwBit = modelComponent.isReadonly() ? null : logicWiresPerPin.get(modelComponent.getReadWritePin()).createReadOnlyEnd();
37 // TODO introduce memoryProcessTime
38 CoreBitVectorMemory<M> mem = new CoreBitVectorMemory<>(timeline, 2, modelComponent.getDefinition(), data, rwBit, address,
39 modelComponent.isReadonly());
40 modelComponent.setCoreModelBinding(mem);