tests/net.mograsim.logic.model.verilog.tests/src/net/mograsim/logic/model/verilog/examples/ExportAm2900.java

   1 package net.mograsim.logic.model.verilog.examples;
   2
   3 import java.io.IOException;
   4 import java.nio.file.Files;
   5 import java.nio.file.Path;
   6 import java.nio.file.Paths;
   7 import java.util.Scanner;
   8 import java.util.Set;
   9 import java.util.stream.Collectors;
  10 import java.util.stream.Stream;
  11
  12 import com.google.gson.JsonElement;
  13
  14 import net.mograsim.logic.core.types.BitVector;
  15 import net.mograsim.logic.model.am2900.Am2900Loader;
  16 import net.mograsim.logic.model.am2900.components.ModelAm2900MPROM;
  17 import net.mograsim.logic.model.am2900.components.ModelAm2900MainMemory;
  18 import net.mograsim.logic.model.am2900.components.ModelAm2900MicroInstructionMemory;
  19 import net.mograsim.logic.model.model.LogicModelModifiable;
  20 import net.mograsim.logic.model.model.components.ModelComponent;
  21 import net.mograsim.logic.model.model.components.Orientation;
  22 import net.mograsim.logic.model.model.components.atomic.ModelBitDisplay;
  23 import net.mograsim.logic.model.model.components.atomic.ModelClock;
  24 import net.mograsim.logic.model.model.components.atomic.ModelClock.ModelClockParams;
  25 import net.mograsim.logic.model.model.components.atomic.ModelFixedOutput;
  26 import net.mograsim.logic.model.model.components.atomic.ModelNandGate;
  27 import net.mograsim.logic.model.model.components.atomic.ModelTextComponent;
  28 import net.mograsim.logic.model.serializing.IdentifyParams;
  29 import net.mograsim.logic.model.serializing.IndirectModelComponentCreator;
  30 import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogComponentDeclarationMapping;
  31 import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogConverter;
  32 import net.mograsim.logic.model.verilog.model.VerilogComponentDeclaration;
  33 import net.mograsim.logic.model.verilog.model.VerilogComponentImplementation;
  34 import net.mograsim.logic.model.verilog.model.signals.IOPort;
  35 import net.mograsim.logic.model.verilog.utils.UnionFind;
  36
  37 public class ExportAm2900
  38 {
  39         public static void main(String[] args) throws IOException
  40         {
  41                 Am2900Loader.setup();
  42                 Path target;
  43                 String rootComponentID;
  44                 try (Scanner sysin = new Scanner(System.in))
  45                 {
  46                         System.out.print("Directory to export Verilog into >");
  47                         target = Paths.get(sysin.nextLine());
  48                         if (!Files.exists(target))
  49                                 Files.createDirectories(target);
  50                         else if (!Files.isDirectory(target))
  51                                 throw new IllegalArgumentException("Target exists and is not a directory");
  52
  53                         System.out.print("Component ID to serialize recursively >");
  54                         rootComponentID = sysin.nextLine();
  55                 }
  56
  57                 if (!Files.exists(target))
  58                         Files.createDirectories(target);
  59                 else if (!Files.isDirectory(target))
  60                         throw new IllegalArgumentException("Target exists and is not a directory");
  61
  62                 LogicModelModifiable model = new LogicModelModifiable();
  63
  64                 Set<ModelComponentToVerilogComponentDeclarationMapping> atomicComponentMappings = Stream.of(//
  65                                 new ModelNandGate(model, 1), //
  66                                 new ModelFixedOutput(model, BitVector.SINGLE_0, null), //
  67                                 new ModelFixedOutput(model, BitVector.SINGLE_1, null), //
  68                                 new ModelClock(model, new ModelClockParams(7000, Orientation.RIGHT)), //
  69                                 new ModelTextComponent(model, "A bus"), //
  70                                 new ModelTextComponent(model, "MPM addr"), //
  71                                 new ModelTextComponent(model, "D bus"), //
  72                                 new ModelAm2900MainMemory(model, null), //
  73                                 new ModelAm2900MPROM(model, null), //
  74                                 new ModelAm2900MicroInstructionMemory(model, null), //
  75                                 new ModelBitDisplay(model, 12), //
  76                                 new ModelBitDisplay(model, 16)//
  77                 ).map(c ->
  78                 {
  79                         String id = c.getIDForSerializing(new IdentifyParams());
  80                         JsonElement params = c.getParamsForSerializingJSON(new IdentifyParams());
  81                         ModelComponentToVerilogComponentDeclarationMapping generateCanonicalDeclarationMapping = ModelComponentToVerilogConverter
  82                                         .generateCanonicalDeclarationMapping(c, new UnionFind<>(), id, params,
  83                                                         ModelComponentToVerilogConverter.sanitizeVerilogID("mgs_" + id + (params.isJsonNull() ? "" : "_" + params)));
  84                         VerilogComponentDeclaration d = generateCanonicalDeclarationMapping.getVerilogComponentDeclaration();
  85                         System.out.println("module " + d.getID() + " "
  86                                         + d.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode).collect(Collectors.joining(", ", "(", ")")) + ";");
  87                         return generateCanonicalDeclarationMapping;
  88                 }).collect(Collectors.toSet());
  89
  90                 ModelComponent root = IndirectModelComponentCreator.createComponent(model, rootComponentID);
  91                 Set<VerilogComponentImplementation> convertResult = ModelComponentToVerilogConverter.convert(atomicComponentMappings, Set.of(root),
  92                                 "mgs_conv_");
  93                 for (VerilogComponentImplementation convertedComponent : convertResult)
  94                         Files.writeString(target.resolve(convertedComponent.getDeclaration().getID() + ".v"), convertedComponent.toVerilogCode());
  95         }
  96 }