Improvements in the ModelComponentToVerilogConverter:
[Mograsim.git] / tests / net.mograsim.logic.model.verilog.tests / src / net / mograsim / logic / model / verilog / examples / ExportAm2900.java
1 package net.mograsim.logic.model.verilog.examples;
2
3 import java.io.IOException;
4 import java.nio.file.Files;
5 import java.nio.file.Path;
6 import java.nio.file.Paths;
7 import java.util.Scanner;
8 import java.util.Set;
9 import java.util.stream.Collectors;
10 import java.util.stream.Stream;
11
12 import com.google.gson.JsonElement;
13
14 import net.mograsim.logic.core.types.BitVector;
15 import net.mograsim.logic.model.am2900.Am2900Loader;
16 import net.mograsim.logic.model.am2900.components.ModelAm2900MPROM;
17 import net.mograsim.logic.model.am2900.components.ModelAm2900MainMemory;
18 import net.mograsim.logic.model.am2900.components.ModelAm2900MicroInstructionMemory;
19 import net.mograsim.logic.model.model.LogicModelModifiable;
20 import net.mograsim.logic.model.model.components.ModelComponent;
21 import net.mograsim.logic.model.model.components.Orientation;
22 import net.mograsim.logic.model.model.components.atomic.ModelBitDisplay;
23 import net.mograsim.logic.model.model.components.atomic.ModelClock;
24 import net.mograsim.logic.model.model.components.atomic.ModelClock.ModelClockParams;
25 import net.mograsim.logic.model.model.components.atomic.ModelFixedOutput;
26 import net.mograsim.logic.model.model.components.atomic.ModelNandGate;
27 import net.mograsim.logic.model.model.components.atomic.ModelTextComponent;
28 import net.mograsim.logic.model.model.components.atomic.ModelTriStateBuffer;
29 import net.mograsim.logic.model.model.components.atomic.ModelTriStateBuffer.ModelTriStateBufferParams;
30 import net.mograsim.logic.model.serializing.IdentifyParams;
31 import net.mograsim.logic.model.serializing.IndirectModelComponentCreator;
32 import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogComponentDeclarationMapping;
33 import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogConverter;
34 import net.mograsim.logic.model.verilog.model.VerilogComponentDeclaration;
35 import net.mograsim.logic.model.verilog.model.VerilogComponentImplementation;
36 import net.mograsim.logic.model.verilog.model.signals.IOPort;
37 import net.mograsim.logic.model.verilog.utils.UnionFind;
38
39 public class ExportAm2900
40 {
41         public static void main(String[] args) throws IOException
42         {
43                 Am2900Loader.setup();
44                 Path target;
45                 String rootComponentID;
46                 try (Scanner sysin = new Scanner(System.in))
47                 {
48                         System.out.print("Directory to export Verilog into >");
49                         target = Paths.get(sysin.nextLine());
50                         if (!Files.exists(target))
51                                 Files.createDirectories(target);
52                         else if (!Files.isDirectory(target))
53                                 throw new IllegalArgumentException("Target exists and is not a directory");
54
55                         System.out.print("Component ID to serialize recursively >");
56                         rootComponentID = sysin.nextLine();
57                 }
58
59                 if (!Files.exists(target))
60                         Files.createDirectories(target);
61                 else if (!Files.isDirectory(target))
62                         throw new IllegalArgumentException("Target exists and is not a directory");
63
64                 LogicModelModifiable model = new LogicModelModifiable();
65
66                 Set<ModelComponentToVerilogComponentDeclarationMapping> atomicComponentMappings = Stream.of(//
67                                 new ModelNandGate(model, 1), //
68                                 new ModelFixedOutput(model, BitVector.SINGLE_0, null), //
69                                 new ModelFixedOutput(model, BitVector.SINGLE_1, null), //
70                                 new ModelTriStateBuffer(model, new ModelTriStateBufferParams(1, Orientation.RIGHT)), //
71                                 new ModelTriStateBuffer(model, new ModelTriStateBufferParams(1, Orientation.RIGHT_ALT)), //
72                                 new ModelTriStateBuffer(model, new ModelTriStateBufferParams(1, Orientation.DOWN)), //
73                                 new ModelTriStateBuffer(model, new ModelTriStateBufferParams(4, Orientation.RIGHT)), //
74                                 new ModelTriStateBuffer(model, new ModelTriStateBufferParams(12, Orientation.RIGHT_ALT)), //
75                                 new ModelTriStateBuffer(model, new ModelTriStateBufferParams(12, Orientation.DOWN)), //
76                                 new ModelTriStateBuffer(model, new ModelTriStateBufferParams(16, Orientation.LEFT)), //
77                                 new ModelTriStateBuffer(model, new ModelTriStateBufferParams(16, Orientation.RIGHT_ALT)), //
78                                 new ModelClock(model, new ModelClockParams(7000, Orientation.RIGHT)), //
79                                 new ModelTextComponent(model, "A bus"), //
80                                 new ModelTextComponent(model, "MPM addr"), //
81                                 new ModelTextComponent(model, "D bus"), //
82                                 new ModelAm2900MainMemory(model, null), //
83                                 new ModelAm2900MPROM(model, null), //
84                                 new ModelAm2900MicroInstructionMemory(model, null), //
85                                 new ModelBitDisplay(model, 12), //
86                                 new ModelBitDisplay(model, 16)//
87                 ).map(c ->
88                 {
89                         String id = c.getIDForSerializing(new IdentifyParams());
90                         JsonElement params = c.getParamsForSerializingJSON(new IdentifyParams());
91                         ModelComponentToVerilogComponentDeclarationMapping generateCanonicalDeclarationMapping = ModelComponentToVerilogConverter
92                                         .generateCanonicalDeclarationMapping(c, new UnionFind<>(), id, params,
93                                                         ModelComponentToVerilogConverter.sanitizeVerilogID("mgs_" + id + (params.isJsonNull() ? "" : "_" + params)));
94                         VerilogComponentDeclaration d = generateCanonicalDeclarationMapping.getVerilogComponentDeclaration();
95                         System.out.println("module " + d.getID() + " "
96                                         + d.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode).collect(Collectors.joining(", ", "(", ")")) + ";");
97                         return generateCanonicalDeclarationMapping;
98                 }).collect(Collectors.toSet());
99
100                 ModelComponent root = IndirectModelComponentCreator.createComponent(model, rootComponentID);
101                 Set<VerilogComponentImplementation> convertResult = ModelComponentToVerilogConverter.convert(atomicComponentMappings, Set.of(root),
102                                 "mgs_conv_");
103                 for (VerilogComponentImplementation convertedComponent : convertResult)
104                         Files.writeString(target.resolve(convertedComponent.getDeclaration().getID() + ".v"), convertedComponent.toVerilogCode());
105         }
106 }