Fixed a bug regarding signal widths

[Mograsim.git] / plugins / net.mograsim.logic.model.verilog / src / net / mograsim / logic / model / verilog / model / signals / Wire.java

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java
index 10e2a50..7e0f2cc 100644 (file)
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java
@@ -9,6 +9,6 @@ public class Wire extends Signal
 
        public String toDeclarationVerilogCode()
        {
-               return "wire [" + getWidth() + ":0] " + getName() + ";";
+               return "wire [" + (getWidth() - 1) + ":0] " + getName() + ";";
        }
 }