Fixed a bug regarding signal widths

[Mograsim.git] / plugins / net.mograsim.logic.model.verilog / src / net / mograsim / logic / model / verilog / model / signals / Input.java

diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
index f80f808..0e8669a 100644 (file)
--- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
+++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java
@@ -10,6 +10,6 @@ public class Input extends IOPort
        @Override
        public String toDeclarationVerilogCode()
        {
-               return "input [" + getWidth() + ":0] " + getName();
+               return "input [" + (getWidth() - 1) + ":0] " + getName();
        }
 }