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Generated Verilog now has a RST "pin"
[Mograsim.git]
/
README.md
2019-10-24
Christian Femers
Changed readme for better status report
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2019-10-24
Christian Femers
Added master build status to readme
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2019-10-23
Christian Femers
Fixed description in readme
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2019-10-06
Daniel Kirschten
Restructured documentation files
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2019-09-25
Daniel Kirschten
Modified README.md a bit; deleted build_from_source.txt
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2019-09-18
Fabian Stemmler
Merge branch 'development' of https://gitlab.lrz.de...
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2019-09-18
Christian Femers
Transferred the simple build instructions into the...
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2019-05-20
Daniel Kirschten
Merged SampleERCP into master
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2019-05-20
Daniel Kirschten
Merged logicui into master
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2019-05-20
Daniel Kirschten
Merged logic into master
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2019-05-20
Christian Femers
Merged master_old into master
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