Mograsim.git
4 years agoMainPreferencePage: Added fields for line widths
Daniel Kirschten [Mon, 18 May 2020 16:42:58 +0000 (18:42 +0200)]
MainPreferencePage: Added fields for line widths

Fixes #3

4 years agoRemoved old commented-out code
Daniel Kirschten [Mon, 18 May 2020 16:41:47 +0000 (18:41 +0200)]
Removed old commented-out code

4 years agoFixed a typo
Daniel Kirschten [Mon, 18 May 2020 16:41:30 +0000 (18:41 +0200)]
Fixed a typo

4 years agoImproved MainPreferencePage:
Daniel Kirschten [Mon, 18 May 2020 16:19:11 +0000 (18:19 +0200)]
Improved MainPreferencePage:

Added preferences for line dashes
Defaults are now properly initialized
Preference names are not hardcoded anymore

4 years agoThe line dash of singlebit wires changes according to their value
Daniel Kirschten [Mon, 18 May 2020 15:05:56 +0000 (17:05 +0200)]
The line dash of singlebit wires changes according to their value

Fixes #2

4 years agoAdded String preferences
Daniel Kirschten [Mon, 18 May 2020 15:00:40 +0000 (17:00 +0200)]
Added String preferences

4 years agoRemoved old TODO
Daniel Kirschten [Mon, 18 May 2020 14:42:20 +0000 (16:42 +0200)]
Removed old TODO

4 years agoAdded the RenderPreference LINE_DASH_IMPROVEMENT_FACTOR
Daniel Kirschten [Mon, 18 May 2020 14:35:25 +0000 (16:35 +0200)]
Added the RenderPreference LINE_DASH_IMPROVEMENT_FACTOR

4 years agoUpdate Eclipse Maven Tycho to 1.7.0
Christian Femers [Tue, 12 May 2020 22:36:39 +0000 (00:36 +0200)]
Update Eclipse Maven Tycho to 1.7.0

4 years agoChanged the IDs of Am2900Simple/Strict to Am2900Teaching/Expert.
Daniel Kirschten [Tue, 12 May 2020 20:07:33 +0000 (22:07 +0200)]
Changed the IDs of Am2900Simple/Strict to Am2900Teaching/Expert.

4 years agoAdded descriptions for both Am2900 variants
Daniel Kirschten [Tue, 12 May 2020 19:58:03 +0000 (21:58 +0200)]
Added descriptions for both Am2900 variants

4 years agoRenamed Am2900Simple/Strict to Am2900Teaching/Expert.
Daniel Kirschten [Tue, 12 May 2020 19:55:44 +0000 (21:55 +0200)]
Renamed Am2900Simple/Strict to Am2900Teaching/Expert.

The machine IDs are unchanged.

4 years agoTurned auto-wrapping on for machines with long descriptions
Daniel Kirschten [Tue, 12 May 2020 19:53:04 +0000 (21:53 +0200)]
Turned auto-wrapping on for machines with long descriptions

4 years agoAdded the possibility for having machine descriptions
Daniel Kirschten [Tue, 12 May 2020 19:32:53 +0000 (21:32 +0200)]
Added the possibility for having machine descriptions

4 years agoChanged MograsimNaturePropertyPage to use MachineCombo
Daniel Kirschten [Tue, 12 May 2020 19:31:48 +0000 (21:31 +0200)]
Changed MograsimNaturePropertyPage to use MachineCombo

4 years agoMade the parent project reference all Mograsim projects
Daniel Kirschten [Mon, 11 May 2020 20:19:07 +0000 (22:19 +0200)]
Made the parent project reference all Mograsim projects

4 years agoAdded HighLevelStates for ram5_12
Daniel Kirschten [Mon, 4 May 2020 21:35:40 +0000 (23:35 +0200)]
Added HighLevelStates for ram5_12

4 years agoCreated a gate-based implementation of ram5_12
Daniel Kirschten [Mon, 4 May 2020 21:26:27 +0000 (23:26 +0200)]
Created a gate-based implementation of ram5_12

4 years agoImplemented the Am2904ShiftInstrDecode gate-based
Daniel Kirschten [Mon, 4 May 2020 18:24:53 +0000 (20:24 +0200)]
Implemented the Am2904ShiftInstrDecode gate-based

4 years agoFixed two bugs in the ModelAm2904ShiftInstrDecode
Daniel Kirschten [Mon, 4 May 2020 18:19:28 +0000 (20:19 +0200)]
Fixed two bugs in the ModelAm2904ShiftInstrDecode

4 years agoFixed horizontalComponentCenter of Am2904RegCTInstrDecode
Daniel Kirschten [Mon, 4 May 2020 18:19:01 +0000 (20:19 +0200)]
Fixed horizontalComponentCenter of Am2904RegCTInstrDecode

4 years agoImplemented Am2904RegCTInstrDecode in gates
Daniel Kirschten [Mon, 4 May 2020 00:00:45 +0000 (02:00 +0200)]
Implemented Am2904RegCTInstrDecode in gates

4 years agoMoved NANDOptimizer to the examples package
Daniel Kirschten [Sat, 2 May 2020 12:26:28 +0000 (14:26 +0200)]
Moved NANDOptimizer to the examples package

4 years agoAdded the missing HighLevelStates for Am2910SP
Daniel Kirschten [Sat, 2 May 2020 12:22:58 +0000 (14:22 +0200)]
Added the missing HighLevelStates for Am2910SP

4 years agoBitVectorSplittingAHLSH now supports minimal and maximal values
Daniel Kirschten [Sat, 2 May 2020 12:22:36 +0000 (14:22 +0200)]
BitVectorSplittingAHLSH now supports minimal and maximal values

4 years agoSnippetDefinintion now delegates to JsonHandler instead of an own Gson
Daniel Kirschten [Sat, 2 May 2020 12:18:23 +0000 (14:18 +0200)]
SnippetDefinintion now delegates to JsonHandler instead of an own Gson

4 years agoWrote a utility optimizing NAND gate count for a given truth table
Daniel Kirschten [Sat, 2 May 2020 11:49:57 +0000 (13:49 +0200)]
Wrote a utility optimizing NAND gate count for a given truth table

4 years agoCreated a NAND-based implementation of Am2910SP
Daniel Kirschten [Sat, 2 May 2020 11:32:16 +0000 (13:32 +0200)]
Created a NAND-based implementation of Am2910SP

4 years agoFixed the height of Am2910RegCntr
Daniel Kirschten [Sat, 2 May 2020 10:57:26 +0000 (12:57 +0200)]
Fixed the height of Am2910RegCntr

4 years agoChanged incrementer layout to have the MSB on top
Daniel Kirschten [Mon, 13 Apr 2020 10:43:41 +0000 (12:43 +0200)]
Changed incrementer layout to have the MSB on top

4 years agoAdjusted layout of the Am2910 to the new Am2910RegCntr
Daniel Kirschten [Sun, 12 Apr 2020 23:23:43 +0000 (01:23 +0200)]
Adjusted layout of the Am2910 to the new Am2910RegCntr

4 years agoMade Am2910RegCntr twice as big
Daniel Kirschten [Sun, 12 Apr 2020 23:19:44 +0000 (01:19 +0200)]
Made Am2910RegCntr twice as big

4 years agoImplemented the Am2910RegCntr gate-based
Daniel Kirschten [Sun, 12 Apr 2020 22:45:05 +0000 (00:45 +0200)]
Implemented the Am2910RegCntr gate-based

4 years agoImplemented a 12-bit decrementer
Daniel Kirschten [Sun, 12 Apr 2020 22:09:48 +0000 (00:09 +0200)]
Implemented a 12-bit decrementer

4 years agoIncluded the XNOR gate into standardComponentIDMapping
Daniel Kirschten [Sun, 12 Apr 2020 22:06:39 +0000 (00:06 +0200)]
Included the XNOR gate into standardComponentIDMapping

4 years agoSwapped the positions of the Y and Z outputs of the halfsubtracter
Daniel Kirschten [Sun, 12 Apr 2020 21:48:45 +0000 (23:48 +0200)]
Swapped the positions of the Y and Z outputs of the halfsubtracter

4 years agoEditor: Created a constant for fast switching between snap 2.5 and 5
Daniel Kirschten [Sun, 12 Apr 2020 21:41:42 +0000 (23:41 +0200)]
Editor: Created a constant for fast switching between snap 2.5 and 5

4 years agoImplemented a "halfsubtracter": a xnor gate that also outputs A or B
Daniel Kirschten [Sun, 12 Apr 2020 21:38:49 +0000 (23:38 +0200)]
Implemented a "halfsubtracter": a xnor gate that also outputs A or B

4 years agoResurrected the XNOR gate
Daniel Kirschten [Sun, 12 Apr 2020 21:23:50 +0000 (23:23 +0200)]
Resurrected the XNOR gate

4 years agoMerged LD and _RLD inputs of ModelAm2910RegCntr into one pin
Daniel Kirschten [Sun, 12 Apr 2020 20:51:29 +0000 (22:51 +0200)]
Merged LD and _RLD inputs of ModelAm2910RegCntr into one pin

4 years agoRedefined PinUsages; cleaned component JSONs
Daniel Kirschten [Sat, 11 Apr 2020 18:19:44 +0000 (20:19 +0200)]
Redefined PinUsages; cleaned component JSONs

4 years agoFixed ReserializeAndVerifyJSONs.changePinUsages
Daniel Kirschten [Sat, 11 Apr 2020 16:01:20 +0000 (18:01 +0200)]
Fixed ReserializeAndVerifyJSONs.changePinUsages

4 years agoAdjusted Am2910 layout to new sel4_12
Daniel Kirschten [Sat, 11 Apr 2020 13:22:54 +0000 (15:22 +0200)]
Adjusted Am2910 layout to new sel4_12

4 years agoImplemented sel4_12 gate-based
Daniel Kirschten [Sat, 11 Apr 2020 13:21:41 +0000 (15:21 +0200)]
Implemented sel4_12 gate-based

4 years agoImplemented a 4-bit sel4
Daniel Kirschten [Sat, 11 Apr 2020 12:36:36 +0000 (14:36 +0200)]
Implemented a 4-bit sel4

4 years agoImplemented sel4
Daniel Kirschten [Sat, 11 Apr 2020 12:25:26 +0000 (14:25 +0200)]
Implemented sel4

4 years agoIndirectModelComponentCreator no longer caches jsonfile: components
Daniel Kirschten [Sat, 11 Apr 2020 12:15:58 +0000 (14:15 +0200)]
IndirectModelComponentCreator no longer caches jsonfile: components

4 years agoFixed a layouting bug in Am2910InstrPLA
Daniel Kirschten [Thu, 9 Apr 2020 23:10:32 +0000 (01:10 +0200)]
Fixed a layouting bug in Am2910InstrPLA

4 years agoSimplified BitVector (de)serializing
Daniel Kirschten [Thu, 9 Apr 2020 16:10:57 +0000 (18:10 +0200)]
Simplified BitVector (de)serializing

4 years agoAdjusted Am2910 to new Am2910InstrPLA layout
Daniel Kirschten [Tue, 7 Apr 2020 22:13:20 +0000 (00:13 +0200)]
Adjusted Am2910 to new Am2910InstrPLA layout

4 years agoRe-layouted the rest of the Am2910InstrPLA
Daniel Kirschten [Tue, 7 Apr 2020 22:11:58 +0000 (00:11 +0200)]
Re-layouted the rest of the Am2910InstrPLA

4 years agoRe-layouted part of the Am2910InstrPLA
Daniel Kirschten [Tue, 7 Apr 2020 21:18:36 +0000 (23:18 +0200)]
Re-layouted part of the Am2910InstrPLA

4 years agoRe-layouted part of the Am2910InstrPLA
Daniel Kirschten [Thu, 2 Apr 2020 15:24:41 +0000 (17:24 +0200)]
Re-layouted part of the Am2910InstrPLA

4 years agoAdded a GCD test case
Daniel Kirschten [Wed, 1 Apr 2020 17:10:03 +0000 (19:10 +0200)]
Added a GCD test case

4 years agoMerge branch 'development' into 'master'
Daniel Kirschten [Tue, 31 Mar 2020 19:05:32 +0000 (21:05 +0200)]
Merge branch 'development' into 'master'

4 years agoFixed dff4_finewe HLS bit order
Daniel Kirschten [Tue, 31 Mar 2020 17:38:33 +0000 (19:38 +0200)]
Fixed dff4_finewe HLS bit order

4 years agoAdjusted layouts of Am2900 and Am2910
Daniel Kirschten [Tue, 31 Mar 2020 16:26:04 +0000 (18:26 +0200)]
Adjusted layouts of Am2900 and Am2910

4 years agoCreated gate-based implementations of an incrementer for 4, 12, 16 bit
Daniel Kirschten [Tue, 31 Mar 2020 16:22:06 +0000 (18:22 +0200)]
Created gate-based implementations of an incrementer for 4, 12, 16 bit

4 years agoCreated a gate-based implementation of dff4_finewe
Daniel Kirschten [Tue, 31 Mar 2020 15:26:18 +0000 (17:26 +0200)]
Created a gate-based implementation of dff4_finewe

4 years agoAdjusted layout of the Am2910 again
Daniel Kirschten [Mon, 30 Mar 2020 20:27:51 +0000 (22:27 +0200)]
Adjusted layout of the Am2910 again

4 years agoCreated a gate-based implementation of dff12
Daniel Kirschten [Mon, 30 Mar 2020 20:25:44 +0000 (22:25 +0200)]
Created a gate-based implementation of dff12

4 years agoAdjusted layout of the Am2910 (again...)
Daniel Kirschten [Mon, 30 Mar 2020 20:11:43 +0000 (22:11 +0200)]
Adjusted layout of the Am2910 (again...)

4 years agoCreated a gate-based implementation of nor12
Daniel Kirschten [Mon, 30 Mar 2020 20:10:21 +0000 (22:10 +0200)]
Created a gate-based implementation of nor12

4 years agoAdjusted layout of the Am2910
Daniel Kirschten [Mon, 30 Mar 2020 19:32:45 +0000 (21:32 +0200)]
Adjusted layout of the Am2910

4 years agoDeleted old hardcoded Am2910InstrPLA
Daniel Kirschten [Mon, 30 Mar 2020 19:26:05 +0000 (21:26 +0200)]
Deleted old hardcoded Am2910InstrPLA

4 years agoInverted the _PL, _MAP, _VECT outputs of the Am2910InstrPLA
Daniel Kirschten [Mon, 30 Mar 2020 17:27:26 +0000 (19:27 +0200)]
Inverted the _PL, _MAP, _VECT outputs of the Am2910InstrPLA

4 years agoAdded a SymbolRenderer for the Am2910InstrPLA
Daniel Kirschten [Mon, 30 Mar 2020 17:21:13 +0000 (19:21 +0200)]
Added a SymbolRenderer for the Am2910InstrPLA

4 years agoImplemented the YF output of the Am2910InstrPLA in gates; w/o layout
Daniel Kirschten [Mon, 30 Mar 2020 16:40:48 +0000 (18:40 +0200)]
Implemented the YF output of the Am2910InstrPLA in gates; w/o layout

4 years agoImplemented the YR output of the Am2910InstrPLA in gates; w/o layout
Daniel Kirschten [Mon, 30 Mar 2020 16:37:13 +0000 (18:37 +0200)]
Implemented the YR output of the Am2910InstrPLA in gates; w/o layout

4 years agoImplemented the STKI1 output of the Am2910InstrPLA in gates; w/o layout
Daniel Kirschten [Mon, 30 Mar 2020 15:44:29 +0000 (17:44 +0200)]
Implemented the STKI1 output of the Am2910InstrPLA in gates; w/o layout

4 years agoImplemented the STKI0 output of the Am2910InstrPLA in gates; w/o layout
Daniel Kirschten [Fri, 27 Mar 2020 19:26:50 +0000 (20:26 +0100)]
Implemented the STKI0 output of the Am2910InstrPLA in gates; w/o layout

4 years agoOrganized imports
Daniel Kirschten [Fri, 27 Mar 2020 19:21:46 +0000 (20:21 +0100)]
Organized imports

4 years agoRestructured the Preferences system
Daniel Kirschten [Fri, 27 Mar 2020 19:06:54 +0000 (20:06 +0100)]
Restructured the Preferences system

4 years agoFixed an endless redraw loop on GTK
Daniel Kirschten [Fri, 27 Mar 2020 16:54:29 +0000 (17:54 +0100)]
Fixed an endless redraw loop on GTK

4 years agoLayouted the gates for YmuPC in Am2910InstrPLA
Daniel Kirschten [Thu, 26 Mar 2020 20:41:18 +0000 (21:41 +0100)]
Layouted the gates for YmuPC in Am2910InstrPLA

4 years agoImplemented the YmuPC output of the Am2910InstrPLA in gates; w/o layout
Daniel Kirschten [Thu, 26 Mar 2020 18:51:30 +0000 (19:51 +0100)]
Implemented the YmuPC output of the Am2910InstrPLA in gates; w/o layout

4 years agoUpdate README to use GitHub Actions Build Status
Christian Femers [Thu, 26 Mar 2020 18:08:17 +0000 (19:08 +0100)]
Update README to use GitHub Actions Build Status

4 years agoImplemented the YD output of the Am2910InstrPLA in gates
Daniel Kirschten [Thu, 26 Mar 2020 17:33:54 +0000 (18:33 +0100)]
Implemented the YD output of the Am2910InstrPLA in gates

4 years agoChanged the line ending to LF in the Resource settings in each project
Daniel Kirschten [Thu, 26 Mar 2020 00:39:55 +0000 (01:39 +0100)]
Changed the line ending to LF in the Resource settings in each project

4 years agoImplemented a part of the Am2910InstrPLA on gate level
Daniel Kirschten [Thu, 26 Mar 2020 00:28:17 +0000 (01:28 +0100)]
Implemented a part of the Am2910InstrPLA on gate level

4 years agoFixed a bug in the ModelAm2910InstrPLA
Daniel Kirschten [Thu, 26 Mar 2020 00:03:49 +0000 (01:03 +0100)]
Fixed a bug in the ModelAm2910InstrPLA

4 years agoReserializeAndVerifyJSONs now uses the unicode escape for mu
Daniel Kirschten [Wed, 25 Mar 2020 22:53:24 +0000 (23:53 +0100)]
ReserializeAndVerifyJSONs now uses the unicode escape for mu

4 years agoAm2910: Changed communication between reg and instrdecode
Daniel Kirschten [Wed, 25 Mar 2020 22:19:27 +0000 (23:19 +0100)]
Am2910: Changed communication between reg and instrdecode

4 years agoGrouped some 4 bit wires in the Am2901
Daniel Kirschten [Wed, 25 Mar 2020 21:08:31 +0000 (22:08 +0100)]
Grouped some 4 bit wires in the Am2901

4 years agoImproved layout of andor414
Daniel Kirschten [Wed, 25 Mar 2020 18:32:31 +0000 (19:32 +0100)]
Improved layout of andor414

4 years agoMade and41 smaller
Daniel Kirschten [Wed, 25 Mar 2020 18:29:36 +0000 (19:29 +0100)]
Made and41 smaller

4 years agoMade the and gate smaller
Daniel Kirschten [Wed, 25 Mar 2020 18:26:20 +0000 (19:26 +0100)]
Made the and gate smaller

4 years agoBuilt a XNOR gate
Daniel Kirschten [Wed, 25 Mar 2020 18:10:54 +0000 (19:10 +0100)]
Built a XNOR gate

4 years agoVerilogExporter now orders interface pins more transparently
Daniel Kirschten [Wed, 25 Mar 2020 18:09:48 +0000 (19:09 +0100)]
VerilogExporter now orders interface pins more transparently

4 years agoChanged how the SubmodelComponent decides whether to show its submodel
Daniel Kirschten [Wed, 25 Mar 2020 18:07:45 +0000 (19:07 +0100)]
Changed how the SubmodelComponent decides whether to show its submodel

4 years agoVerilogExporter now "hands through" a clk signal
Daniel Kirschten [Sun, 1 Mar 2020 16:26:28 +0000 (17:26 +0100)]
VerilogExporter now "hands through" a clk signal

to avoid combinatorial loops

4 years agoMerge pull request #11 from MaisiKoleni/config-gh-actions
Daniel Kirschten [Tue, 11 Feb 2020 16:15:33 +0000 (17:15 +0100)]
Merge pull request #11 from MaisiKoleni/config-gh-actions

GitHub Actions setup to test and build Mograsim automatically

4 years agoGH-Actions clone submodules
Christian Femers [Tue, 11 Feb 2020 01:25:29 +0000 (02:25 +0100)]
GH-Actions clone submodules

4 years agoConfigure GitHub Actions for Mograsim
Christian Femers [Tue, 11 Feb 2020 01:15:32 +0000 (02:15 +0100)]
Configure GitHub Actions for Mograsim

4 years agoGenerated Verilog now has a RST "pin"
Daniel Kirschten [Tue, 4 Feb 2020 10:54:19 +0000 (11:54 +0100)]
Generated Verilog now has a RST "pin"

4 years agoLogicCoreAdapter now makes global statistics for gate count
Daniel Kirschten [Tue, 4 Feb 2020 10:53:34 +0000 (11:53 +0100)]
LogicCoreAdapter now makes global statistics for gate count

4 years agoModelComponentTestbench's Switches/Displays are named after their pins
Daniel Kirschten [Mon, 6 Jan 2020 22:38:22 +0000 (23:38 +0100)]
ModelComponentTestbench's Switches/Displays are named after their pins

4 years agoModelComponentTestbench works again
Daniel Kirschten [Mon, 6 Jan 2020 22:32:08 +0000 (23:32 +0100)]
ModelComponentTestbench works again

4 years agoVerilogExporter: Components are now named
Daniel Kirschten [Sun, 5 Jan 2020 23:13:31 +0000 (00:13 +0100)]
VerilogExporter: Components are now named

4 years agoVerilogExporter: Fixed serializing components without params
Daniel Kirschten [Sun, 5 Jan 2020 22:40:32 +0000 (23:40 +0100)]
VerilogExporter: Fixed serializing components without params