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Fixed a bug regarding signal widths
[Mograsim.git]
/
tests
/
net.mograsim.logic.model.verilog.tests
/
src
/
net
/
mograsim
/
2021-01-14
Daniel Kirschten
ModelComponentToVerilogConverter can now convert TriSta...
tree
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commitdiff
2021-01-14
Daniel Kirschten
Improvements in the ModelComponentToVerilogConverter:
tree
|
commitdiff
2021-01-14
Daniel Kirschten
ExportAm2900 now prints module headers for "atomic...
tree
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commitdiff
2021-01-14
Daniel Kirschten
ModelComponentToVerilogConverter almost supports connec...
tree
|
commitdiff
2021-01-14
Daniel Kirschten
First version of the new Verilog exporter
tree
|
commitdiff