net.mograsim.machine/src/net/mograsim/machine/standard/memory/CoreWordAddressableMemory.java

   1 package net.mograsim.machine.standard.memory;
   2
   3 import java.util.List;
   4
   5 import net.mograsim.logic.core.components.BasicCoreComponent;
   6 import net.mograsim.logic.core.timeline.Timeline;
   7 import net.mograsim.logic.core.timeline.TimelineEventHandler;
   8 import net.mograsim.logic.core.types.Bit;
   9 import net.mograsim.logic.core.types.BitVector;
  10 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
  11 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
  12 import net.mograsim.machine.MainMemoryDefinition;
  13
  14 /**
  15  * A memory component that only allows access to words of a specific width
  16  */
  17 public class CoreWordAddressableMemory extends BasicCoreComponent
  18 {
  19         private final WordAddressableMemory memory;
  20         private final static Bit read = Bit.ONE;
  21
  22         private ReadWriteEnd data;
  23         private ReadEnd rWBit, address, clock;
  24
  25         /**
  26          * @param data    The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
  27          *                a memory word
  28          * @param rWBit   The value of the 0th bit dictates the mode: 0: Write, 1: Read
  29          * @param address The bits of this ReadEnd address the memory cell to read/write
  30          */
  31         public CoreWordAddressableMemory(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
  32                         ReadEnd rWBit, ReadEnd address, ReadEnd clock)
  33         {
  34                 super(timeline, processTime);
  35                 if(data.width() != definition.getCellWidth())
  36                         throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.width()));
  37                 if(rWBit.width() != 1)
  38                         throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.width()));
  39                 if(address.width() != definition.getMemoryAddressBits())
  40                         throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.width()));
  41                 this.data = data;
  42                 this.rWBit = rWBit;
  43                 this.address = address;
  44                 this.clock = clock;
  45                 data.registerObserver(this);
  46                 rWBit.registerObserver(this);
  47                 address.registerObserver(this);
  48                 clock.registerObserver(this);
  49
  50                 memory = new WordAddressableMemory(definition);
  51         }
  52
  53         @Override
  54         protected TimelineEventHandler compute()
  55         {
  56                 if(clock.getValue() != Bit.ONE)
  57                         return null;
  58
  59                 if (!address.hasNumericValue())
  60                 {
  61                         if (read.equals(rWBit.getValue()))
  62                                 return e -> data.feedSignals(Bit.U.toVector(data.width()));
  63                         return e -> data.clearSignals();
  64                 }
  65                 long addressed = address.getUnsignedValue();
  66                 if (read.equals(rWBit.getValue()))
  67                 {
  68                         BitVector storedData = memory.getCell(addressed);
  69                         return e -> data.feedSignals(storedData);
  70                 }
  71                 else
  72                 {
  73                         BitVector transData = data.getValues();
  74                         return e ->
  75                         {
  76                                 data.clearSignals();
  77                                 memory.setCell(addressed, transData);
  78                         };
  79                 }
  80         }
  81
  82         @Override
  83         public List<ReadEnd> getAllInputs()
  84         {
  85                 return List.of(data, rWBit, address);
  86         }
  87
  88         @Override
  89         public List<ReadWriteEnd> getAllOutputs()
  90         {
  91                 return List.of(data);
  92         }
  93 }