Fixed test setup and added support for high level state access
[Mograsim.git] / net.mograsim.logic.core /
2019-09-01 Daniel KirschtenSlight improvements of Wire#fuse(...)
2019-09-01 Daniel KirschtenRemove legacy, broken Connector; rename Merger&Splitter...
2019-09-01 Daniel KirschtenMerge branch 'fusebug' into development
2019-09-01 Daniel KirschtenFixed fusebug
2019-09-01 Daniel KirschtenMerge branch 'fusebug' into development
2019-09-01 Fabian StemmlerMerge branch 'fusebug' of https://gitlab.lrz.de/lrr...
2019-09-01 Fabian StemmlerFixed issue with Wire fusion
2019-09-01 Christian FemersCreated model for the logic Clock
2019-08-28 Fabian StemmlerRemoved superfluous main method in BitVector
2019-08-28 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
2019-08-28 Fabian StemmlerFixed getUnsignedValue() in BitVector
2019-08-27 Fabian StemmlerFixed BitVector#getUnsignedValue();It no longer returns...
2019-08-27 Fabian StemmlerMerge branch 'development' of
2019-08-27 Daniel KirschtenUndo renaming of BitVector's length to width
2019-08-26 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
2019-08-26 Daniel KirschtenFurther renaming of length to width
2019-08-26 Christian FemersMy proposal for resolving add92039f433cd315f2087da9c1a0...
2019-08-26 Christian FemersRefactored Wire and finally renamed length to width
2019-08-26 Christian FemersRefactored BitVector and added test cases
2019-08-25 Fabian StemmlerAdded methods for conversion between BitVector and...
2019-08-23 Christian FemersAdded binary check method
2019-08-23 Christian FemersMoved main memory to machine module
2019-08-23 Christian FemersAdded factory methods for integers
2019-08-22 Fabian StemmlerAdded memory in logic.core to exported packages
2019-08-21 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
2019-08-21 Fabian StemmlerAdded GUIComponent for Word Addressable Memory
2019-08-20 Daniel KirschtenMerge remote-tracking branch 'origin/development' into...
2019-08-20 Fabian StemmlerMoved WordAddressableMemoryComponent to new package
2019-08-19 Fabian StemmlerAdded prototype component for main memory
2019-08-13 Christian FemersRemoved Util because it is not used anymore (for a...
2019-08-10 Daniel KirschtenGUIBitDisplay and GUIManualSwitch now support logicWidt...
2019-07-18 Christian FemersAdded single Bit constants
2019-07-15 Daniel KirschtenFinished renaming logic.ui to logic.model
2019-07-13 Fabian StemmlerMerge branch 'development' of
2019-07-11 Christian FemersRefactored BitVector methods to resolve ambiguity
2019-07-03 Daniel KirschtenOrganized imports + cleaned MANIFEST.MF
2019-06-30 Daniel KirschtenAdded MSB first versions of parse() and toString()
2019-06-30 Daniel KirschtenMoved sanity check to make more sense
2019-06-29 Christian FemersFixed ManualSwitch concerning U and added Bit methods
2019-06-26 Daniel KirschtenConstructor of BitVector now is fail-fast for bits...
2019-06-26 Fabian StemmlerAdded forceValues(...) method to Wire
2019-06-25 Daniel KirschtenChanges in the preference system
2019-06-25 Daniel KirschtenCreated net.mograsim.preferences
2019-06-25 Daniel KirschtenCleaned project references and MANIFEST.mf Bundle-Vendo...
2019-06-24 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
2019-06-23 Daniel KirschtenCleaned up:
2019-06-23 Christian FemersCompletely changed the structure and switched to Eclips...
2019-06-21 Daniel KirschtenMade Wire.fuse(Wire, Wire, int, int int) public
2019-06-21 Fabian StemmlerFusing Wires will no longer initialize Wires with value U
2019-06-21 Fabian StemmlerQuickfix for Wire.fuse(...)
2019-06-19 Daniel KirschtenMerge commit '28314e7a9a3c3ebfcc4db8e9f1875507063ae6e6...
2019-06-18 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
2019-06-18 Fabian StemmlerLogic Wire bits can now be fused together (Wire.fuse...
2019-06-05 Fabian StemmlerFixed nand and nor gate to work with more than two...
2019-06-04 Fabian StemmlerAdded nand and nor gate due to popular demand
2019-06-03 Daniel KirschtenOrganized imports in all three projects
2019-06-03 Daniel KirschtenWires now can have a name
2019-06-02 Daniel KirschtenMade Timeline.timeCmp public again
2019-06-02 Fabian StemmlerBitDisplay, ManualSwitch now Observable. More Docs...
2019-06-02 Fabian StemmlerCleanup; Cleared warnings in the logic core
2019-06-02 Fabian StemmlerGeneralized WireObserver to LogicObserver
2019-05-30 Daniel KirschtenRenamed project folders to match the respective project...