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VerilogExporter now orders interface pins more transparently
[Mograsim.git] / plugins / net.mograsim.logic.model.am2900 / src / net / mograsim / logic / model / examples / VerilogExporter.java
2020-03-25 Daniel KirschtenVerilogExporter now orders interface pins more transpar... blob | commitdiff | raw
2020-03-25 Daniel KirschtenVerilogExporter now "hands through" a clk signal blob | commitdiff | raw | diff to current
2020-02-11 Daniel KirschtenMerge pull request #11 from MaisiKoleni/config-gh-actions blob | commitdiff | raw | diff to current
2020-02-04 Daniel KirschtenGenerated Verilog now has a RST "pin" blob | commitdiff | raw | diff to current
2020-01-05 Daniel KirschtenVerilogExporter: Components are now named blob | commitdiff | raw | diff to current
2020-01-05 Daniel KirschtenVerilogExporter: Fixed serializing components without... blob | commitdiff | raw | diff to current
2020-01-05 Daniel KirschtenAdded a class for exporting component JSONs to Verilog blob | commitdiff | raw | diff to current
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