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Added the RenderPreference LINE_DASH_IMPROVEMENT_FACTOR
2020-05-18
Daniel Kirschten
Added the RenderPreference LINE_DASH_IMPROVEMENT_FACTOR
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2020-05-12
Daniel Kirschten
Changed the IDs of Am2900Simple/Strict to Am2900Teaching...
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2020-05-12
Daniel Kirschten
Added descriptions for both Am2900 variants
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2020-05-12
Daniel Kirschten
Renamed Am2900Simple/Strict to Am2900Teaching/Expert.
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2020-05-12
Daniel Kirschten
Turned auto-wrapping on for machines with long descriptions
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2020-05-12
Daniel Kirschten
Added the possibility for having machine descriptions
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2020-05-12
Daniel Kirschten
Changed MograsimNaturePropertyPage to use MachineCombo
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2020-05-11
Daniel Kirschten
Made the parent project reference all Mograsim projects
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2020-05-04
Daniel Kirschten
Added HighLevelStates for ram5_12
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2020-05-04
Daniel Kirschten
Created a gate-based implementation of ram5_12
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2020-05-04
Daniel Kirschten
Implemented the Am2904ShiftInstrDecode gate-based
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2020-05-04
Daniel Kirschten
Fixed two bugs in the ModelAm2904ShiftInstrDecode
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2020-05-04
Daniel Kirschten
Fixed horizontalComponentCenter of Am2904RegCTInstrDecode
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2020-05-04
Daniel Kirschten
Implemented Am2904RegCTInstrDecode in gates
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2020-05-02
Daniel Kirschten
Moved NANDOptimizer to the examples package
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2020-05-02
Daniel Kirschten
Added the missing HighLevelStates for Am2910SP
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2020-05-02
Daniel Kirschten
BitVectorSplittingAHLSH now supports minimal and maximal...
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2020-05-02
Daniel Kirschten
SnippetDefinintion now delegates to JsonHandler instead...
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2020-05-02
Daniel Kirschten
Wrote a utility optimizing NAND gate count for a given...
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2020-05-02
Daniel Kirschten
Created a NAND-based implementation of Am2910SP
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2020-05-02
Daniel Kirschten
Fixed the height of Am2910RegCntr
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2020-04-13
Daniel Kirschten
Changed incrementer layout to have the MSB on top
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2020-04-12
Daniel Kirschten
Adjusted layout of the Am2910 to the new Am2910RegCntr
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2020-04-12
Daniel Kirschten
Made Am2910RegCntr twice as big
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2020-04-12
Daniel Kirschten
Implemented the Am2910RegCntr gate-based
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2020-04-12
Daniel Kirschten
Implemented a 12-bit decrementer
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2020-04-12
Daniel Kirschten
Included the XNOR gate into standardComponentIDMapping
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2020-04-12
Daniel Kirschten
Swapped the positions of the Y and Z outputs of the...
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2020-04-12
Daniel Kirschten
Editor: Created a constant for fast switching between...
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2020-04-12
Daniel Kirschten
Implemented a "halfsubtracter": a xnor gate that also...
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2020-04-12
Daniel Kirschten
Resurrected the XNOR gate
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2020-04-12
Daniel Kirschten
Merged LD and _RLD inputs of ModelAm2910RegCntr into...
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2020-04-11
Daniel Kirschten
Redefined PinUsages; cleaned component JSONs
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2020-04-11
Daniel Kirschten
Fixed ReserializeAndVerifyJSONs.changePinUsages
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2020-04-11
Daniel Kirschten
Adjusted Am2910 layout to new sel4_12
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2020-04-11
Daniel Kirschten
Implemented sel4_12 gate-based
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2020-04-11
Daniel Kirschten
Implemented a 4-bit sel4
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2020-04-11
Daniel Kirschten
Implemented sel4
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2020-04-11
Daniel Kirschten
IndirectModelComponentCreator no longer caches jsonfile...
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2020-04-09
Daniel Kirschten
Fixed a layouting bug in Am2910InstrPLA
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2020-04-09
Daniel Kirschten
Simplified BitVector (de)serializing
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2020-04-07
Daniel Kirschten
Adjusted Am2910 to new Am2910InstrPLA layout
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2020-04-07
Daniel Kirschten
Re-layouted the rest of the Am2910InstrPLA
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2020-04-07
Daniel Kirschten
Re-layouted part of the Am2910InstrPLA
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2020-04-02
Daniel Kirschten
Re-layouted part of the Am2910InstrPLA
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2020-04-01
Daniel Kirschten
Added a GCD test case
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2020-03-31
Daniel Kirschten
Merge branch 'development' into 'master'
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2020-03-31
Daniel Kirschten
Fixed dff4_finewe HLS bit order
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2020-03-31
Daniel Kirschten
Adjusted layouts of Am2900 and Am2910
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2020-03-31
Daniel Kirschten
Created gate-based implementations of an incrementer...
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2020-03-31
Daniel Kirschten
Created a gate-based implementation of dff4_finewe
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2020-03-30
Daniel Kirschten
Adjusted layout of the Am2910 again
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2020-03-30
Daniel Kirschten
Created a gate-based implementation of dff12
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2020-03-30
Daniel Kirschten
Adjusted layout of the Am2910 (again...)
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2020-03-30
Daniel Kirschten
Created a gate-based implementation of nor12
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2020-03-30
Daniel Kirschten
Adjusted layout of the Am2910
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2020-03-30
Daniel Kirschten
Deleted old hardcoded Am2910InstrPLA
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2020-03-30
Daniel Kirschten
Inverted the _PL, _MAP, _VECT outputs of the Am2910InstrPLA
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2020-03-30
Daniel Kirschten
Added a SymbolRenderer for the Am2910InstrPLA
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2020-03-30
Daniel Kirschten
Implemented the YF output of the Am2910InstrPLA in...
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2020-03-30
Daniel Kirschten
Implemented the YR output of the Am2910InstrPLA in...
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2020-03-30
Daniel Kirschten
Implemented the STKI1 output of the Am2910InstrPLA...
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2020-03-27
Daniel Kirschten
Implemented the STKI0 output of the Am2910InstrPLA...
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2020-03-27
Daniel Kirschten
Organized imports
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2020-03-27
Daniel Kirschten
Restructured the Preferences system
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2020-03-27
Daniel Kirschten
Fixed an endless redraw loop on GTK
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2020-03-26
Daniel Kirschten
Layouted the gates for YmuPC in Am2910InstrPLA
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2020-03-26
Daniel Kirschten
Implemented the YmuPC output of the Am2910InstrPLA...
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2020-03-26
Daniel Kirschten
Implemented the YD output of the Am2910InstrPLA in...
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2020-03-26
Daniel Kirschten
Changed the line ending to LF in the Resource settings...
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2020-03-26
Daniel Kirschten
Implemented a part of the Am2910InstrPLA on gate level
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2020-03-26
Daniel Kirschten
Fixed a bug in the ModelAm2910InstrPLA
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2020-03-25
Daniel Kirschten
ReserializeAndVerifyJSONs now uses the unicode escape...
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2020-03-25
Daniel Kirschten
Am2910: Changed communication between reg and instrdecode
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2020-03-25
Daniel Kirschten
Grouped some 4 bit wires in the Am2901
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2020-03-25
Daniel Kirschten
Improved layout of andor414
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2020-03-25
Daniel Kirschten
Made and41 smaller
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2020-03-25
Daniel Kirschten
Made the and gate smaller
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2020-03-25
Daniel Kirschten
Built a XNOR gate
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2020-03-25
Daniel Kirschten
VerilogExporter now orders interface pins more transparently
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2020-03-25
Daniel Kirschten
Changed how the SubmodelComponent decides whether to...
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2020-03-25
Daniel Kirschten
VerilogExporter now "hands through" a clk signal
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2020-02-11
Daniel Kirschten
Merge pull request #11 from MaisiKoleni/config-gh-actions
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2020-02-04
Daniel Kirschten
Generated Verilog now has a RST "pin"
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2020-02-04
Daniel Kirschten
LogicCoreAdapter now makes global statistics for gate...
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2020-01-06
Daniel Kirschten
ModelComponentTestbench's Switches/Displays are named...
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2020-01-06
Daniel Kirschten
ModelComponentTestbench works again
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2020-01-05
Daniel Kirschten
VerilogExporter: Components are now named
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2020-01-05
Daniel Kirschten
VerilogExporter: Fixed serializing components without...
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2020-01-05
Daniel Kirschten
Added a class for exporting component JSONs to Verilog
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2019-11-25
Daniel Kirschten
Made ModelAm2904RegCTInstrDecode more robust against...
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2019-11-25
Daniel Kirschten
Improved JavaJsonLineCounter a bit
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2019-11-15
Daniel Kirschten
Switched to using logical U for mnemonic X to avoid...
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2019-11-15
Daniel Kirschten
Changed mnemonic X to use BitVector X; added X for...
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2019-11-13
Daniel Kirschten
Changed microinstruction column titles to English
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2019-11-13
Daniel Kirschten
Adjusted some param titles
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2019-11-13
Daniel Kirschten
Added short titles for MPM columns
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2019-11-13
Daniel Kirschten
Added possibility to swap column tooltip and title...
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2019-11-13
Daniel Kirschten
Updated getting_started.md
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2019-10-30
Daniel Kirschten
Fixed the documentation
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