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Added the possibility for having machine descriptions
2020-05-12 Daniel KirschtenAdded the possibility for having machine descriptions
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2020-05-12 Daniel KirschtenChanged MograsimNaturePropertyPage to use MachineCombo
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2020-05-11 Daniel KirschtenMade the parent project reference all Mograsim projects
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2020-05-04 Daniel KirschtenAdded HighLevelStates for ram5_12
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2020-05-04 Daniel KirschtenCreated a gate-based implementation of ram5_12
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2020-05-04 Daniel KirschtenImplemented the Am2904ShiftInstrDecode gate-based
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2020-05-04 Daniel KirschtenFixed two bugs in the ModelAm2904ShiftInstrDecode
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2020-05-04 Daniel KirschtenFixed horizontalComponentCenter of Am2904RegCTInstrDecode
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2020-05-04 Daniel KirschtenImplemented Am2904RegCTInstrDecode in gates
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2020-05-02 Daniel KirschtenMoved NANDOptimizer to the examples package
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2020-05-02 Daniel KirschtenAdded the missing HighLevelStates for Am2910SP
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2020-05-02 Daniel KirschtenBitVectorSplittingAHLSH now supports minimal and maximal...
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2020-05-02 Daniel KirschtenSnippetDefinintion now delegates to JsonHandler instead...
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2020-05-02 Daniel KirschtenWrote a utility optimizing NAND gate count for a given...
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2020-05-02 Daniel KirschtenCreated a NAND-based implementation of Am2910SP
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2020-05-02 Daniel KirschtenFixed the height of Am2910RegCntr
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2020-04-13 Daniel KirschtenChanged incrementer layout to have the MSB on top
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2020-04-12 Daniel KirschtenAdjusted layout of the Am2910 to the new Am2910RegCntr
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2020-04-12 Daniel KirschtenMade Am2910RegCntr twice as big
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2020-04-12 Daniel KirschtenImplemented the Am2910RegCntr gate-based
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2020-04-12 Daniel KirschtenImplemented a 12-bit decrementer
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2020-04-12 Daniel KirschtenIncluded the XNOR gate into standardComponentIDMapping
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2020-04-12 Daniel KirschtenSwapped the positions of the Y and Z outputs of the...
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2020-04-12 Daniel KirschtenEditor: Created a constant for fast switching between...
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2020-04-12 Daniel KirschtenImplemented a "halfsubtracter": a xnor gate that also...
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2020-04-12 Daniel KirschtenResurrected the XNOR gate
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2020-04-12 Daniel KirschtenMerged LD and _RLD inputs of ModelAm2910RegCntr into...
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2020-04-11 Daniel KirschtenRedefined PinUsages; cleaned component JSONs
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2020-04-11 Daniel KirschtenFixed ReserializeAndVerifyJSONs.changePinUsages
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2020-04-11 Daniel KirschtenAdjusted Am2910 layout to new sel4_12
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2020-04-11 Daniel KirschtenImplemented sel4_12 gate-based
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2020-04-11 Daniel KirschtenImplemented a 4-bit sel4
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2020-04-11 Daniel KirschtenImplemented sel4
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2020-04-11 Daniel KirschtenIndirectModelComponentCreator no longer caches jsonfile...
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2020-04-09 Daniel KirschtenFixed a layouting bug in Am2910InstrPLA
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2020-04-09 Daniel KirschtenSimplified BitVector (de)serializing
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2020-04-07 Daniel KirschtenAdjusted Am2910 to new Am2910InstrPLA layout
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2020-04-07 Daniel KirschtenRe-layouted the rest of the Am2910InstrPLA
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2020-04-07 Daniel KirschtenRe-layouted part of the Am2910InstrPLA
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2020-04-02 Daniel KirschtenRe-layouted part of the Am2910InstrPLA
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2020-04-01 Daniel KirschtenAdded a GCD test case
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2020-03-31 Daniel KirschtenMerge branch 'development' into 'master'
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2020-03-31 Daniel KirschtenFixed dff4_finewe HLS bit order
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2020-03-31 Daniel KirschtenAdjusted layouts of Am2900 and Am2910
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2020-03-31 Daniel KirschtenCreated gate-based implementations of an incrementer...
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2020-03-31 Daniel KirschtenCreated a gate-based implementation of dff4_finewe
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2020-03-30 Daniel KirschtenAdjusted layout of the Am2910 again
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2020-03-30 Daniel KirschtenCreated a gate-based implementation of dff12
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2020-03-30 Daniel KirschtenAdjusted layout of the Am2910 (again...)
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2020-03-30 Daniel KirschtenCreated a gate-based implementation of nor12
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2020-03-30 Daniel KirschtenAdjusted layout of the Am2910
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2020-03-30 Daniel KirschtenDeleted old hardcoded Am2910InstrPLA
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2020-03-30 Daniel KirschtenInverted the _PL, _MAP, _VECT outputs of the Am2910InstrPLA
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2020-03-30 Daniel KirschtenAdded a SymbolRenderer for the Am2910InstrPLA
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2020-03-30 Daniel KirschtenImplemented the YF output of the Am2910InstrPLA in...
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2020-03-30 Daniel KirschtenImplemented the YR output of the Am2910InstrPLA in...
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2020-03-30 Daniel KirschtenImplemented the STKI1 output of the Am2910InstrPLA...
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2020-03-27 Daniel KirschtenImplemented the STKI0 output of the Am2910InstrPLA...
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2020-03-27 Daniel KirschtenOrganized imports
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2020-03-27 Daniel KirschtenRestructured the Preferences system
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2020-03-27 Daniel KirschtenFixed an endless redraw loop on GTK
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2020-03-26 Daniel KirschtenLayouted the gates for YmuPC in Am2910InstrPLA
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2020-03-26 Daniel KirschtenImplemented the YmuPC output of the Am2910InstrPLA...
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2020-03-26 Daniel KirschtenImplemented the YD output of the Am2910InstrPLA in...
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2020-03-26 Daniel KirschtenChanged the line ending to LF in the Resource settings...
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2020-03-26 Daniel KirschtenImplemented a part of the Am2910InstrPLA on gate level
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2020-03-26 Daniel KirschtenFixed a bug in the ModelAm2910InstrPLA
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2020-03-25 Daniel KirschtenReserializeAndVerifyJSONs now uses the unicode escape...
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2020-03-25 Daniel KirschtenAm2910: Changed communication between reg and instrdecode
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2020-03-25 Daniel KirschtenGrouped some 4 bit wires in the Am2901
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2020-03-25 Daniel KirschtenImproved layout of andor414
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2020-03-25 Daniel KirschtenMade and41 smaller
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2020-03-25 Daniel KirschtenMade the and gate smaller
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2020-03-25 Daniel KirschtenBuilt a XNOR gate
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2020-03-25 Daniel KirschtenVerilogExporter now orders interface pins more transparently
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2020-03-25 Daniel KirschtenChanged how the SubmodelComponent decides whether to...
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2020-03-25 Daniel KirschtenVerilogExporter now "hands through" a clk signal
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2020-02-11 Daniel KirschtenMerge pull request #11 from MaisiKoleni/config-gh-actions
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2020-02-04 Daniel KirschtenGenerated Verilog now has a RST "pin"
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2020-02-04 Daniel KirschtenLogicCoreAdapter now makes global statistics for gate...
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2020-01-06 Daniel KirschtenModelComponentTestbench's Switches/Displays are named...
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2020-01-06 Daniel KirschtenModelComponentTestbench works again
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2020-01-05 Daniel KirschtenVerilogExporter: Components are now named
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2020-01-05 Daniel KirschtenVerilogExporter: Fixed serializing components without...
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2020-01-05 Daniel KirschtenAdded a class for exporting component JSONs to Verilog
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2019-11-25 Daniel KirschtenMade ModelAm2904RegCTInstrDecode more robust against...
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2019-11-25 Daniel KirschtenImproved JavaJsonLineCounter a bit
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2019-11-15 Daniel KirschtenSwitched to using logical U for mnemonic X to avoid...
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2019-11-15 Daniel KirschtenChanged mnemonic X to use BitVector X; added X for...
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2019-11-13 Daniel KirschtenChanged microinstruction column titles to English
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2019-11-13 Daniel KirschtenAdjusted some param titles
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2019-11-13 Daniel KirschtenAdded short titles for MPM columns
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2019-11-13 Daniel KirschtenAdded possibility to swap column tooltip and title...
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2019-11-13 Daniel KirschtenUpdated getting_started.md
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2019-10-30 Daniel KirschtenFixed the documentation
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2019-10-30 Daniel KirschtenAdded a (very elaborately _cough_) explanation for...
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2019-10-30 Daniel KirschtenAdded TestGCD
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2019-10-30 Daniel KirschtenMicroInstructionMemoryParser and MainMemoryParser now...
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2019-10-30 Daniel KirschtenMade hardcoded components slower to fix a timing bug...
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2019-10-30 Daniel KirschtenFixed a timing bug in SimpleRectangularHardcodedModelCompone...
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