VerilogExporter now orders interface pins more transparently
[Mograsim.git] / plugins / net.mograsim.logic.model.am2900 /
2020-03-25 Daniel KirschtenVerilogExporter now orders interface pins more transpar...
2020-03-25 Daniel KirschtenVerilogExporter now "hands through" a clk signal
2020-02-11 Daniel KirschtenMerge pull request #11 from MaisiKoleni/config-gh-actions
2020-02-04 Daniel KirschtenGenerated Verilog now has a RST "pin"
2020-02-04 Daniel KirschtenLogicCoreAdapter now makes global statistics for gate...
2020-01-06 Daniel KirschtenModelComponentTestbench's Switches/Displays are named...
2020-01-05 Daniel KirschtenVerilogExporter: Components are now named
2020-01-05 Daniel KirschtenVerilogExporter: Fixed serializing components without...
2020-01-05 Daniel KirschtenAdded a class for exporting component JSONs to Verilog
2019-11-25 Daniel KirschtenMade ModelAm2904RegCTInstrDecode more robust against...
2019-11-15 Daniel KirschtenChanged mnemonic X to use BitVector X; added X for...
2019-11-13 Daniel KirschtenChanged microinstruction column titles to English
2019-11-13 Daniel KirschtenAdjusted some param titles
2019-11-13 Daniel KirschtenAdded short titles for MPM columns
2019-10-30 Daniel KirschtenMade hardcoded components slower to fix a timing bug...
2019-10-30 Daniel KirschtenFixed a bug in the Am2900
2019-10-30 Daniel KirschtenAm2900Machine now resets registers in strict mode too
2019-10-12 Daniel KirschtenImproved labels of Am2901's subcomponents
2019-10-12 Daniel KirschtenMade FixedOutput smaller
2019-10-12 Fabian StemmlerMade Am2900 Bus BitDisplays prettier
2019-10-11 Fabian StemmlerMicroInstructionDefinition now also has simple Mnemonic...
2019-10-07 Daniel KirschtenAdded register for PC / BZ
2019-10-07 Daniel KirschtenAdded register for IR
2019-10-07 Daniel KirschtenAdded register for muIR
2019-10-07 Daniel KirschtenAdded Am2910 registers
2019-10-07 Daniel KirschtenFixed the same bug in some Am2900-specific ModelComponents
2019-10-07 Daniel KirschtenChanged Modelram5_12's HLS-IDs to have a trailing .q
2019-10-06 Daniel KirschtenMerge remote-tracking branch 'origin/development' into...
2019-10-06 Daniel KirschtenAdded Am2904 registers
2019-10-06 Daniel KirschtenMade muSR / MSR accessible bit-wise
2019-10-06 Daniel KirschtenRe-added Am2901 registers
2019-10-06 Daniel KirschtenRestructured register system
2019-10-06 Daniel KirschtenReplaced micro symbols with Unicode escape \u00b5
2019-10-06 Christian FemersAdded RegisterGroups for MachineDefinition
2019-10-05 Daniel KirschtenMerge branch threads into development
2019-10-05 Daniel KirschtenWrote TODO
2019-10-04 Daniel KirschtenAdded simple version of Am2900Machine
2019-10-02 Daniel KirschtenAdded register listeners
2019-10-02 Daniel KirschtenFixed a NullPointerException in Modeldff4_finewe
2019-10-02 Daniel KirschtenMerge remote-tracking branch 'origin/development' into...
2019-10-02 Daniel KirschtenChanged getCurrentMicroInstructionAddress to use HighLe...
2019-10-01 Daniel KirschtenAdded missing package to model.am2900's MANIFEST
2019-10-01 Daniel KirschtenMerge remote-tracking branch 'origin/development' into...
2019-09-30 Daniel KirschtenAm2900Machine now has registers
2019-09-30 Daniel KirschtenMerge branch 'machines-are-launch-configs' into development
2019-09-30 Fabian StemmlerActiveInstructionChangedListener moved to Machine and...
2019-09-26 Daniel KirschtenMade Clock slow enough for the slowest microinstruction...
2019-09-26 Daniel KirschtenUpdated project references; also plugin.core no longer...
2019-09-26 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
2019-09-26 Daniel KirschtenRemoved debug sysouts to make the plugin "silent"
2019-09-26 Daniel KirschtenMade MemoryView to an Editor
2019-09-26 Fabian StemmlerSet reasonable default values for Am2900 MicroInstructions
2019-09-26 Fabian StemmlerAdded MnemonicFamilyBuilder and set most Mnemonics...
2019-09-26 Daniel KirschtenFixed Am2900Machine#reset (broke when deleting clock...
2019-09-25 Daniel KirschtenRemoved the clock ManualSwitches and made the clock...
2019-09-25 Daniel KirschtenBZ/PC and IR now get written at the rising clock edge
2019-09-25 Daniel KirschtenReserialized components
2019-09-25 Daniel KirschtenMade Am2900 memory reads work if Am2901Dest=QREG ...
2019-09-25 Daniel KirschtenFixed two small bugs in the two Delegating...Handlers:
2019-09-25 Daniel KirschtenMade clock overridable by a ManualSwitch
2019-09-25 Daniel KirschtenReserialized components
2019-09-25 Daniel KirschtenMerge remote-tracking branch 'origin/development' into...
2019-09-24 Fabian StemmlerMerge branch 'development' of
2019-09-24 Fabian StemmlerAdded clock to Am2900
2019-09-24 Daniel KirschtenMerge remote-tracking branch 'origin/development' into...
2019-09-24 Christian FemersAdded id to machine definition (was only set in the...
2019-09-18 Daniel KirschtenRAM reads no longer cause X on the data bus:
2019-09-17 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
2019-09-17 Daniel KirschtenCleaned up memory stuff
2019-09-17 Fabian StemmlerMerge branch 'development' of
2019-09-17 Fabian StemmlerMicroInstructionMemory editor can now open and save...
2019-09-17 Daniel KirschtenCorrected RAM control signal timing
2019-09-17 Daniel KirschtenMade Am2900 work again in ModelComponentTestbench
2019-09-17 Daniel KirschtenReserialized components
2019-09-16 Fabian StemmlerMerge branch 'development' of https://gitlab.lrz.de...
2019-09-16 Daniel KirschtenRemoved overkill version attribute from standardCompone...
2019-09-16 Daniel KirschtenAm2900 now has HighLevelStates
2019-09-16 Daniel KirschtenFixed Clock polarities to values where the Am2900 works
2019-09-16 Daniel KirschtenFixed Am2900MicroInstructionMemoryDefinition's maximal...
2019-09-16 Daniel KirschtenFixed a FixedOutput in Am2900
2019-09-16 Daniel KirschtenMerge branch 'cont-integr-2' into 'development'
2019-09-16 Christian FemersThe final restructured version for automatic build...